diff options
| author | Jan Kiszka <jan.kiszka@siemens.com> | 2020-05-18 07:57:22 +0200 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2020-05-19 14:41:13 +0530 |
| commit | c02712a7484918648e5dd09c092035c7eeb7794a (patch) | |
| tree | c039b0a9f623eefc534fb3dbffceacee041d61a7 /board/ti/am65x | |
| parent | 6cfd09d4ed43ee401cc16f1dffabe7911b603380 (diff) | |
arm: mach-k3: Enable dcache in SPL
Add support for enabling dcache already in SPL. It accelerates the boot
and resolves the risk to run into unaligned 64-bit accesses.
Based on original patch by Lokesh Vulta.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/ti/am65x')
| -rw-r--r-- | board/ti/am65x/evm.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index a610879424..2da7db9f09 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -69,11 +69,13 @@ int dram_init_banksize(void) /* Bank 0 declares the memory available in the DDR low region */ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x80000000; + gd->ram_size = 0x100000000; #endif return 0; |