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authorKumar Gala <galak@kernel.crashing.org>2008-08-27 01:03:42 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-08-27 11:43:52 -0500
commitc360d9b970fbb9c13744c355879671165bbb9b9e (patch)
tree8b421f634303b379282bf63e99741d6d1fa5e101 /board/stxgp3
parent8e55313b7ae12352a343f9b9962e662dbd897187 (diff)
FSL DDR: Convert STXGP3 to new DDR code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/stxgp3')
-rw-r--r--board/stxgp3/Makefile12
-rw-r--r--board/stxgp3/ddr.c70
-rw-r--r--board/stxgp3/stxgp3.c6
-rw-r--r--board/stxgp3/u-boot.lds1
4 files changed, 83 insertions, 6 deletions
diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile
index 325d6d57221..5a68f11e7d0 100644
--- a/board/stxgp3/Makefile
+++ b/board/stxgp3/Makefile
@@ -25,10 +25,14 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o flash.o law.o tlb.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+COBJS-y += $(BOARD).o
+COBJS-y += law.o
+COBJS-y += tlb.o
+COBJS-y += flash.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c
new file mode 100644
index 00000000000..45372f42713
--- /dev/null
+++ b/board/stxgp3/ddr.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+
+static void
+get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
+}
+
+
+unsigned int
+fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+
+void
+fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0) {
+ i2c_address = SPD_EEPROM_ADDRESS;
+ }
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c
index 218e8053f1d..c80f1b3810b 100644
--- a/board/stxgp3/stxgp3.c
+++ b/board/stxgp3/stxgp3.c
@@ -32,7 +32,9 @@
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
+#include <asm/mmu.h>
#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#include <spd_sdram.h>
@@ -292,7 +294,9 @@ initdram (int board_type)
}
#endif
- dram_size = spd_sdram ();
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC)
/* Initialize and enable DDR ECC.
diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds
index 9cc499747fe..d5363be5a57 100644
--- a/board/stxgp3/u-boot.lds
+++ b/board/stxgp3/u-boot.lds
@@ -76,7 +76,6 @@ SECTIONS
cpu/mpc85xx/cpu_init.o (.text)
cpu/mpc85xx/cpu.o (.text)
cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/spd_sdram.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)