hummingboard: Remove unused directory

The 'mx6-microsom' directory was only used for the previous mx6solo
hummingboard support, which has been removed in favour of the SPL
version.

Remove the remaining piece of the old mx6solo hummingboard support.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

3 files changed, 0 insertions, 183 deletions

diff --git a/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
deleted file mode 100644
index 40747abbdb2..00000000000
--- a/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 SolidRun ltd.
- * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* ZQ Calibrations */
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
-/* write leveling */
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052
-/*
- * DQS gating, read delay, write delay calibration values
- * based on calibration compare of 0x00ffff00
- */
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034
-/* read data bit delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-/* Complete calibration by forced measurement */
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-
-/*
- * MMDC init:
- * in DDR3, 32-bit mode, only MMDC0 is initiated:
- */
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040
-
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63
-
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
-/* CS0_END - 0x2fffffff, 512M  */
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-
-/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */
-DATA 4, 0x021b0400, 0x11420000
-
-/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */
-DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
-
-/*
- * Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C
- * MR2
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
-/* MR3 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-/* MR1 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
-/* MR0 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-/* final DDR setup */
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/solidrun/mx6-microsom/clocks.cfg b/board/solidrun/mx6-microsom/clocks.cfg
deleted file mode 100644
index 12888113fbf..00000000000
--- a/board/solidrun/mx6-microsom/clocks.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 SolidRun ltd.
- * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1    --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
deleted file mode 100644
index f92fc19de47..00000000000
--- a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 SolidRun ltd.
- * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * DDR3 settings
- * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 32 bits	x16/x32
- */
-/* DDR IO TYPE */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-/* Clock */
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
-/* Address */
-DATA 4, MX6_IOM_DRAM_CAS, 0x00000010
-DATA 4, MX6_IOM_DRAM_RAS, 0x00000010
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010
-/* Control */
-DATA 4, MX6_IOM_DRAM_RESET, 0x00000010
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010
-
-/*
- * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS,
- * CMOS mode saves power, but have less timing margin in case of DDR
- * timing issue on your board you can try DDR_MODE:  [= 0x00020000]
- */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
-
-/*
- * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS,
- * CMOS mode saves power, but have less timing margin in case of DDR
- * timing issue on your board you can try DDR_MODE:  [= 0x00020000]
- */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000