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authorPeter Tyser <ptyser@xes-inc.com>2008-11-11 10:17:10 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-12-03 22:46:42 -0600
commita2cd50ed6ef0ac6b127b3d6db756979a8336718d (patch)
treea8064eb08a501fdecadfb50af56f646c90be0f3a /board/socrates
parente57f0fa1333cdf3ca36110aac2900712a5f82976 (diff)
85xx: Add CPU 2 errata workaround to all 8548 boards
All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
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