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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-22 07:42:19 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-09-23 01:00:23 +0900 |
commit | c72f4d4c2ebb3be9797ef6cd7dcbc2124c825f7a (patch) | |
tree | 4a31e92876cb55753ac16aac95fb2dbe57236b3d /board/socrates | |
parent | 0298f4c0032e2ba7e417aacc66da98887a2e0a5b (diff) |
ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'board/socrates')
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