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authorSergei Poselenov <sposelenov@emcraft.com>2008-06-06 15:42:41 +0200
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-06-11 00:30:09 -0500
commit59abd15b43cab7a4d19de4ba0943837d9555f7ba (patch)
tree3cac646776cda715f7bc54c7c7566f9e7d5965db /board/socrates/law.c
parent740280e68ccc0b971e613face7eaaa8bd1382b8c (diff)
Socrates: Added FPGA mapping. LAWs and TLBs cleanup.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Diffstat (limited to 'board/socrates/law.c')
-rw-r--r--board/socrates/law.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/board/socrates/law.c b/board/socrates/law.c
index 5f4b8ca4f90..ab9a99439f1 100644
--- a/board/socrates/law.c
+++ b/board/socrates/law.c
@@ -33,13 +33,12 @@
/*
* LAW(Local Access Window) configuration:
*
- * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x0000_0000 0x2fff_ffff DDR 512M
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xc000_0000 0xc00f_ffff FPGA 1M
+ * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR)
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xf800_0000 0xf80f_ffff BCSR 1M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ * 0xfc00_0000 0xffff_ffff FLASH 64M
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
@@ -49,9 +48,11 @@
struct law_entry law_table[] = {
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+ SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+#if defined(CFG_FPGA_BASE)
+ SET_LAW_ENTRY(5, CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);