* Patch by Marc Singer, 29 May 2003:LABEL_2003_05_31_2115

  Fixed rarp boot method for IA32 and other little-endian CPUs.

* Patch by Marc Singer, 28 May 2003:
  Added port I/O commands.

* Patch by Matthew McClintock, 28 May 2003
  - cpu/mpc824x/start.S: fix relocation code when booting from RAM
  - minor patches for utx8245

* Patch by Daniel Engström, 28 May 2003:
  x86 update

* Patch by Dave Ellis, 9 May 2003 + 27 May 2003:
  add nand flash support to SXNI855T configuration
  fix/extend nand flash support:
  - fix 'nand erase' command so does not erase bad blocks
  - fix 'nand write' command so does not write to bad blocks
  - fix nand_probe() so handles no flash detected properly
  - add doc/README.nand
  - add .jffs2 and .oob options to nand read/write
  - add 'nand bad' command to list bad blocks
  - add 'clean' option to 'nand erase' to write JFFS2 clean markers
  - make NAND read/write faster

* Patch by Rune Torgersen, 23 May 2003:
  Update for MPC8266ADS board

7 files changed, 1822 insertions, 0 deletions

diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile
new file mode 100644
index 00000000000..53217c380e4
--- /dev/null
+++ b/board/sc520_spunk/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= sc520_spunk.o flash.o
+SOBJS	:= sc520_spunk_asm.o sc520_spunk_asm16.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/sc520_spunk/config.mk b/board/sc520_spunk/config.mk
new file mode 100644
index 00000000000..2253815647a
--- /dev/null
+++ b/board/sc520_spunk/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+
+TEXT_BASE = 0x387c0000
diff --git a/board/sc520_spunk/flash.c b/board/sc520_spunk/flash.c
new file mode 100644
index 00000000000..66ef720660d
--- /dev/null
+++ b/board/sc520_spunk/flash.c
@@ -0,0 +1,813 @@
+/*
+ * (C) Copyright 2002, 2003
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ * 
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <asm/ic/sc520.h>
+
+#define PROBE_BUFFER_SIZE 1024
+static unsigned char buffer[PROBE_BUFFER_SIZE];
+
+
+#define SC520_MAX_FLASH_BANKS  1
+#define SC520_FLASH_BANK0_BASE 0x38000000  /* BOOTCS */
+#define SC520_FLASH_BANKSIZE   0x8000000
+
+#define A29LV641DH_SIZE        0x800000
+#define A29LV641DH_SECTORS     128
+
+#define A29LV641MH_SIZE        0x800000
+#define A29LV641MH_SECTORS     128
+
+#define I28F320J3A_SIZE        0x400000
+#define I28F320J3A_SECTORS     32
+
+#define I28F640J3A_SIZE        0x800000
+#define I28F640J3A_SECTORS     64
+
+#define I28F128J3A_SIZE        0x1000000
+#define I28F128J3A_SECTORS     128
+
+flash_info_t    flash_info[SC520_MAX_FLASH_BANKS];
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+/*-----------------------------------------------------------------------
+ */
+
+
+static u32 _probe_flash(u32 addr, u32 bw, int il)
+{
+	u32 result=0;
+	
+	/* First do an unlock cycle for the benefit of
+	 * devices that need it */
+	
+	switch (bw) {
+		
+	case 1:
+		*(volatile u8*)(addr+0x5555) = 0xaa;
+		*(volatile u8*)(addr+0x2aaa) = 0x55;
+		*(volatile u8*)(addr+0x5555) = 0x90;
+		
+		/* Read vendor */
+		result = *(volatile u8*)addr;
+		result <<= 16;
+		
+		/* Read device */
+		result |= *(volatile u8*)(addr+2);
+		
+		/* Return device to data mode */
+		*(volatile u8*)addr = 0xff;
+		*(volatile u8*)(addr+0x5555), 0xf0;  
+		break;
+		
+	case 2:
+		*(volatile u16*)(addr+0xaaaa) = 0xaaaa;
+		*(volatile u16*)(addr+0x5554) = 0x5555;
+		
+		/* Issue identification command */
+		if (il == 2) {
+			*(volatile u16*)(addr+0xaaaa) = 0x9090;
+			
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u8*)(addr+2);
+			
+			/* Return device to data mode */
+			*(volatile u16*)addr =  0xffff;
+			*(volatile u16*)(addr+0xaaaa), 0xf0f0;  
+			
+		} else {
+			*(volatile u8*)(addr+0xaaaa) = 0x90;
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u16*)(addr+2);
+			
+			/* Return device to data mode */
+			*(volatile u8*)addr = 0xff;
+			*(volatile u8*)(addr+0xaaaa), 0xf0;  			
+		}
+		
+		break;
+		
+	 case 4:
+		*(volatile u32*)(addr+0x5554) = 0xaaaaaaaa;
+		*(volatile u32*)(addr+0xaaa8) = 0x55555555;
+		
+		switch (il) {
+		case 1:
+			/* Issue identification command */
+			*(volatile u8*)(addr+0x5554) = 0x90;
+			
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+		
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+			
+			/* Return device to data mode */
+			*(volatile u8*)addr =  0xff;
+			*(volatile u8*)(addr+0x5554), 0xf0;  
+			break;
+			
+		case 2:
+			/* Issue identification command */
+			*(volatile u32*)(addr + 0x5554) = 0x00900090;
+			
+			/* Read vendor */
+			result = *(volatile u16*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u16*)(addr+4);
+			
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0x00ff00ff;
+			*(volatile u32*)(addr+0x5554), 0x00f000f0;  
+			break;
+			
+		case 4:
+			/* Issue identification command */
+			*(volatile u32*)(addr+0x5554) = 0x90909090;
+			
+			/* Read vendor */
+			result = *(volatile u8*)addr;
+			result <<= 16;
+			
+			/* Read device */
+			result |= *(volatile u8*)(addr+4);
+			
+			/* Return device to data mode */
+			*(volatile u32*)addr =  0xffffffff;
+			*(volatile u32*)(addr+0x5554), 0xf0f0f0f0; 
+			break;
+		}
+		break;
+	}
+	
+	
+	
+	return result;
+}
+
+extern int _probe_flash_end;
+asm ("_probe_flash_end:\n"
+     ".long 0\n");
+
+static int identify_flash(unsigned address, int width)
+{
+	int is;	
+	int device;
+	int vendor;	
+	int size;
+	unsigned res;
+	
+	u32 (*_probe_flash_ptr)(u32 a, u32 bw, int il);
+	
+	size = (unsigned)&_probe_flash_end - (unsigned)_probe_flash; 
+	
+	if (size > PROBE_BUFFER_SIZE) {
+		printf("_probe_flash() routine too large (%d) %p - %p\n",
+		       size, &_probe_flash_end, _probe_flash);
+		return 0;
+	}
+	
+	memcpy(buffer, _probe_flash, size);
+	_probe_flash_ptr = (void*)buffer;
+	
+	is = disable_interrupts();
+	res = _probe_flash_ptr(address, width, 1);
+	if (is) {
+		enable_interrupts();
+	}
+	
+	
+        vendor = res >> 16;
+	device = res & 0xffff;
+	
+		
+	return res;
+}
+
+ulong flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+	
+	for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
+		unsigned id;
+		ulong flashbase = 0;
+		int sectsize = 0; 
+		
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = SC520_FLASH_BANK0_BASE;
+			break;
+		default:
+			panic("configured to many flash banks!\n");
+		}
+		
+		id = identify_flash(flashbase, 2);
+		switch (id) {
+		case 0x000122d7:
+			/* 29LV641DH */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV640U & FLASH_TYPEMASK);
+			
+			flash_info[i].size = A29LV641DH_SIZE;
+			flash_info[i].sector_count = A29LV641DH_SECTORS;
+			sectsize = A29LV641DH_SIZE/A29LV641DH_SECTORS;
+			printf("Bank %d: AMD 29LV641DH\n", i);
+			break;
+			
+		case 0x0001227E:
+			/* 29LV641MH */
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_DL640 & FLASH_TYPEMASK);
+			
+			flash_info[i].size = A29LV641MH_SIZE;
+			flash_info[i].sector_count = A29LV641MH_SECTORS;
+			sectsize = A29LV641MH_SIZE/A29LV641MH_SECTORS;
+			printf("Bank %d: AMD 29LV641MH\n", i);
+			break;
+			
+		case 0x00890016:
+			/* 28F320J3A */
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F320J3A & FLASH_TYPEMASK);
+			
+			flash_info[i].size = I28F320J3A_SIZE;
+			flash_info[i].sector_count = I28F320J3A_SECTORS;
+			sectsize = I28F320J3A_SIZE/I28F320J3A_SECTORS;
+			printf("Bank %d: Intel 28F320J3A\n", i);
+			break;
+			
+		case 0x00890017:
+			/* 28F640J3A */
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
+			
+			flash_info[i].size = I28F640J3A_SIZE;
+			flash_info[i].sector_count = I28F640J3A_SECTORS;
+			sectsize = I28F640J3A_SIZE/I28F640J3A_SECTORS;
+			printf("Bank %d: Intel 28F640J3A\n", i);
+			break;
+			
+		case 0x00890018:
+			/* 28F128J3A */
+			flash_info[i].flash_id =
+				(INTEL_MANUFACT & FLASH_VENDMASK) |
+				(INTEL_ID_28F128J3A & FLASH_TYPEMASK);
+			
+			flash_info[i].size = I28F128J3A_SIZE;
+			flash_info[i].sector_count = I28F128J3A_SECTORS;
+			sectsize = I28F128J3A_SIZE/I28F128J3A_SECTORS;
+			printf("Bank %d: Intel 28F128J3A\n", i);
+			break;
+			
+		default:
+			printf("Bank %d have unknown flash %08x\n", i, id);
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			continue;
+		}
+		
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * sectsize;
+		}
+		size += flash_info[i].size;
+		
+		flash_protect(FLAG_PROTECT_CLEAR,
+			      flash_info[i].start[0],
+			       flash_info[i].start[0] + flash_info[i].size - 1,
+			      &flash_info[i]);
+	}
+	
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      i386boot_start,
+		      i386boot_end,
+		      &flash_info[0]);
+#ifdef CFG_ENV_ADDR
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		      &flash_info[0]);
+#endif	
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+	
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf("INTEL: ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (INTEL_ID_28F320J3A & FLASH_TYPEMASK):
+			printf("1x I28F320J3A (32Mbit)\n");
+			break;
+		case (INTEL_ID_28F640J3A & FLASH_TYPEMASK):
+			printf("1x I28F640J3A (64Mbit)\n");
+			break;
+		case (INTEL_ID_28F128J3A & FLASH_TYPEMASK):
+			printf("1x I28F128J3A (128Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+		
+		break;
+		
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf("AMD:   ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (AMD_ID_LV640U & FLASH_TYPEMASK):
+			printf("1x AMD29LV641DH (64Mbit)\n");
+			break;
+		case (AMD_ID_DL640 & FLASH_TYPEMASK):
+			printf("1x AMD29LV641MH (64Mbit)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			goto done;
+			break;
+		}
+		
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+	
+	
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+	
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	
+	done:
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+static u32 _amd_erase_flash(u32 addr, u32 sector)
+{
+	unsigned elapsed;
+	
+	/* Issue erase */
+	*(volatile u16*)(addr + 0xaaaa) = 0x00AA;
+	*(volatile u16*)(addr + 0x5554) = 0x0055;
+	*(volatile u16*)(addr + 0xaaaa) = 0x0080;
+	/* And one unlock */
+	*(volatile u16*)(addr + 0xaaaa) = 0x00AA;
+	*(volatile u16*)(addr + 0x5554) = 0x0055;
+	/* Sector erase command comes last */
+	*(volatile u16*)(addr + sector) = 0x0030;
+	
+	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = 0;
+	while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) {
+		
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+			*(volatile u16*)(addr) = 0x00f0;
+			return 1;			
+		}
+	}
+	
+	*(volatile u16*)(addr) = 0x00f0;
+	
+	return 0;
+}
+
+extern int _amd_erase_flash_end;
+asm ("_amd_erase_flash_end:\n"
+     ".long 0\n");
+
+/* this needs to be inlined, the SWTMRMMILLI register is reset by each read */
+#define __udelay(delay) \
+{	\
+	unsigned micro; \
+	unsigned milli=0; \
+	\
+	micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+         \
+	for (;;) { \
+		\
+		milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+		micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \
+		\
+		if ((delay) <= (micro + (milli * 1000))) { \
+			break; \
+		} \
+	} \
+} while (0) 
+
+static u32 _intel_erase_flash(u32 addr, u32 sector)
+{	
+	unsigned elapsed;
+	
+	*(volatile u16*)(addr + sector) = 0x0050;   /* clear status register */
+	*(volatile u16*)(addr + sector) = 0x0020;   /* erase setup */
+	*(volatile u16*)(addr + sector) = 0x00D0;   /* erase confirm */
+
+	
+	/* Wait at least 80us - let's wait 1 ms */
+	__udelay(1000);
+	
+	elapsed = 0;
+	while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) {
+		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+			*(volatile u16*)(addr + sector) = 0x00B0;  /* suspend erase      */
+			*(volatile u16*)(addr + sector) = 0x00FF;  /* reset to read mode */
+			return 1;			
+		}
+	}
+	
+	*(volatile u16*)(addr + sector) = 0x00FF;  /* reset to read mode */
+	
+	return 0;
+}
+
+
+extern int _intel_erase_flash_end;
+asm ("_intel_erase_flash_end:\n"
+     ".long 0\n");
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	u32 (*_erase_flash_ptr)(u32 a, u32 so);
+	int prot;
+	int sect;
+	unsigned size;
+	
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+	
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_erase_flash_end - (unsigned)_amd_erase_flash; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_erase_flash() routine too large (%d) %p - %p\n",
+			       size, &_amd_erase_flash_end, _amd_erase_flash);
+			return 0;
+		}
+		
+		memcpy(buffer, _amd_erase_flash, size);
+		_erase_flash_ptr = (void*)buffer;
+	
+	} else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_intel_erase_flash_end - (unsigned)_intel_erase_flash; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_intel_erase_flash() routine too large (%d) %p - %p\n",
+			       size, &_intel_erase_flash_end, _intel_erase_flash);
+			return 0;
+		}
+		
+		memcpy(buffer, _intel_erase_flash, size);
+		_erase_flash_ptr = (void*)buffer;
+	} else {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+		
+	
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		
+		if (info->protect[sect] == 0) { /* not protected */
+			int res;
+			int flag;
+			
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+			
+			res = _erase_flash_ptr(info->start[0], info->start[sect]-info->start[0]);
+			
+			/* re-enable interrupts if necessary */
+			if (flag) {
+				enable_interrupts();
+			}
+			
+			
+			if (res) {
+				printf("Erase timed out, sector %d\n", sect);
+				return res;
+			}
+			
+			putc('.');			
+		}		
+	}
+
+	
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int _amd_write_word(unsigned start, unsigned dest, unsigned data)
+{
+	volatile u16 *addr2 = (u16*)start;
+	volatile u16 *dest2 = (u16*)dest;
+	volatile u16 *data2 = (u16*)&data;
+	int i;
+	unsigned elapsed;
+	
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile u16*)dest) & (u16)data) != (u16)data) {
+		return 2;
+	}
+	
+	for (i = 0; i < 2; i++) {
+		
+		
+		addr2[0x5555] = 0x00AA;
+		addr2[0x2aaa] = 0x0055;
+		addr2[0x5555] = 0x00A0;
+		
+		dest2[i] = (data >> (i*16)) & 0xffff;
+		
+		elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+		elapsed = 0;
+		
+		/* data polling for D7 */
+		while ((dest2[i] & 0x0080) != (data2[i] & 0x0080)) {
+			elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+			if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+				addr2[i] = 0x00f0;
+				return 1;			
+			}
+		}
+	}
+	
+	addr2[i] = 0x00f0;
+	
+	return 0;
+}
+
+extern int _amd_write_word_end;
+asm ("_amd_write_word_end:\n"
+     ".long 0\n");
+
+
+
+static int _intel_write_word(unsigned start, unsigned dest, unsigned data)
+{
+	int i;
+	unsigned elapsed;
+	
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((volatile u16*)dest) & (u16)data) != (u16)data) {
+		return 2;
+	}
+	
+	for (i = 0; i < 2; i++) {
+		
+		*(volatile u16*)(dest+2*i) = 0x0040; /* write setup */		
+		*(volatile u16*)(dest+2*i) = (data >> (i*16)) & 0xffff;
+		
+		elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+		elapsed = 0;
+		
+		/* data polling for D7 */
+		while ((*(volatile u16*)dest & 0x0080) != 0x0080) {
+			elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+			if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+				*(volatile u16*)dest = 0x00ff;
+				return 1;			
+			}
+		}
+	}
+	
+	*(volatile u16*)dest = 0x00ff;
+	
+	
+	return 0;
+
+}
+
+extern int _intel_write_word_end;
+asm ("_intel_write_word_end:\n"
+     ".long 0\n");
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 3 - Unsupported flash type
+ */
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+	int flag;
+	u32 (*_write_word_ptr)(unsigned start, unsigned dest, unsigned data);
+	unsigned size;
+	
+	if ((info->flash_id & FLASH_VENDMASK) == (AMD_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_amd_write_word_end - (unsigned)_amd_write_word; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_amd_write_word() routine too large (%d) %p - %p\n",
+			       size, &_amd_write_word_end, _amd_write_word);
+			return 0;
+		}
+		
+		memcpy(buffer, _amd_write_word, size);
+		_write_word_ptr = (void*)buffer;
+	
+	} else if ((info->flash_id & FLASH_VENDMASK) == (INTEL_MANUFACT & FLASH_VENDMASK)) {
+		size = (unsigned)&_intel_write_word_end - (unsigned)_intel_write_word; 
+		
+		if (size > PROBE_BUFFER_SIZE) {
+			printf("_intel_write_word() routine too large (%d) %p - %p\n",
+			       size, &_intel_write_word_end, _intel_write_word);
+			return 0;
+		}
+		
+		memcpy(buffer, _intel_write_word, size);
+		_write_word_ptr = (void*)buffer;
+	} else {
+		printf ("Can't program unknown flash type - aborted\n");
+		return 3;
+	}
+
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+	
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data |= (*(uchar *)cp) << (8*i);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data |= *src++ << (8*i);
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data |= (*(uchar *)cp)  << (8*i);
+		}
+		
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		
+		rc = _write_word_ptr(info->start[0], wp, data);
+		
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp += 4;
+	}
+	
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+			       
+		for (i=0; i<4; ++i) {
+			data |= *src++ << (8*i);
+		}
+		
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		rc = _write_word_ptr(info->start[0], wp, data);
+		
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+		if (rc != 0) {
+			return rc;
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+	
+	if (cnt == 0) {
+		return 0;
+	}
+	
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data |= *src++ << (8*i);
+		--cnt;
+	}
+	
+	for (; i<4; ++i, ++cp) {
+		data |= (*(uchar *)cp) << (8*i);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	rc = _write_word_ptr(info->start[0], wp, data);
+	
+	/* re-enable interrupts if necessary */
+	if (flag) {
+		enable_interrupts();
+	}
+	
+	return rc;
+	
+}
+
+
diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
new file mode 100644
index 00000000000..962e04e4418
--- /dev/null
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -0,0 +1,686 @@
+/*
+ * 
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <ssi.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+
+
+/* ------------------------------------------------------------------------- */
+
+	
+/* 
+ * Theory:
+ * We first set up all IRQs to be non-pci, edge triggered,
+ * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets 
+ * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
+ * as needed. Whe choose the irqs to gram from a configurable list
+ * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
+ * such as 0 thngas will not work)
+ */
+
+static void irq_init(void)
+{
+	/* disable global interrupt mode */
+	write_mmcr_byte(SC520_PICICR, 0x40); 
+	
+	/* set all irqs to edge */
+	write_mmcr_byte(SC520_MPICMODE, 0x00);
+	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
+	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+	
+	/* active low polarity on PIC interrupt pins, 
+	 *  active high polarity on all other irq pins */
+	write_mmcr_word(SC520_INTPINPOL, 0x0000);
+
+	/* set irq number mapping */
+	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */       
+	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
+	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
+	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */ 
+	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
+	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
+	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
+	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
+	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
+	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
+	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */ 
+	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6);              /* Set Synchronius serial INT to IRQ6*/
+	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
+	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
+	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
+	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
+	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
+	
+	write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);            /* Set internal UART2 INT to IRQ4 */
+	write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);            /* Set internal UART2 INT to IRQ3 */
+	
+	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7);             /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
+	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14);            /* Set GPIRQ1 (CF IRQ) to IRQ14 */
+	write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5);             /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */ 
+	write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);     /* disbale GIRQ4 ( IRR IRQ ) */
+	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ5 */
+	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ6 */
+	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ7 */
+	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ8 */
+	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ9 */
+	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ2 */
+	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED);     /* disable GPIRQ10 */          
+	
+	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);               /* Map PCI hostbridge INT to NMI */
+	write_mmcr_word(SC520_ECCMAP, 0x100);                   /* Map SDRAM ECC failure INT to NMI */
+ 
+}
+
+	
+/* PCI stuff */
+static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CFG_FIRST_PCI_IRQ,
+		CFG_SECOND_PCI_IRQ,
+		CFG_THIRD_PCI_IRQ,
+		CFG_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+	
+	char tmp_pin;	
+	int pin;
+	
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+	
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
+	
+	
+       
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 6:  /* ETH0 */		  
+		pin+=SC520_PCI_INTA;
+		break;
+		
+	case 7:  /* ETH1 */
+		pin+=SC520_PCI_INTB;
+		break;
+		
+	case 8:  /* Crypto */
+		pin+=SC520_PCI_INTC;
+		break;
+		
+	case 9: /* PMC slot */
+		pin+=SC520_PCI_INTD;
+		break;
+		
+	case 10: /* PC-Card */
+		
+		if (version < 10) {			
+			pin+=SC520_PCI_INTD;
+		} else {
+			pin+=SC520_PCI_INTC;
+		}
+		break;
+		
+	default: 
+		return;
+	}
+	
+	pin&=3; /* wrap around */
+	
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */		
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { 
+			return;
+		}
+		next_irq_index++;
+	}
+
+	
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 
+					   sc520_pci_ints[pin]);
+	}
+#if 0	
+	printf("fixup_irq: device %d pin %c irq %d\n", 
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+#endif
+}
+
+
+static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose, 
+					      pci_dev_t dev, struct pci_config_table *te)
+{
+	u32 io_base;
+	u32 temp;
+	
+	pciauto_config_device(hose, dev);
+	
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
+	pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
+	pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
+	pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
+	pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
+	
+	pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */ 
+	pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */ 
+	/* route MF0 to ~INT and MF3 to IRQ7 
+	 * reserve all others */
+	pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002); 
+	pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
+	pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
+	
+	if (te->device != 0xac56) {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
+		pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
+	} else {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
+	}
+	pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
+	
+	
+	pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
+	io_base &= ~0xfL;
+	
+	writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
+	writel(0, io_base+0x10);     /* CLKRUN default */
+	writel(0, io_base+0x20);     /* CLKRUN default */
+	
+}
+
+
+
+static struct pci_config_table pci_sc520_spunk_config_table[] = {
+	{ 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, 
+	{ 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} }, 
+	{ 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
+};
+
+static struct pci_controller sc520_spunk_hose = {
+	fixup_irq: pci_sc520_spunk_fixup_irq,
+	config_table: pci_sc520_spunk_config_table,
+	first_busno: 0x00,
+	last_busno: 0xff,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&sc520_spunk_hose);
+}
+
+
+/* set up the ISA bus timing and system address mappings */
+static void bus_init(void)
+{
+	/* versions 
+	 * 0   Hyglo versions 0.95 and 0.96 (large baords)
+	 * ??  Hyglo version 0.97 (small board)
+	 * 10  Spunk board
+	 */
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	if (version) {
+		/* set up the GP IO pins (for the Spunk board) */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); 	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0,  0x000f);  	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x000f); 	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);  	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0xc0);  		/* set the CS pin function reg */	
+		write_mmcr_byte(SC520_CLKSEL, 0x70);
+		
+		write_mmcr_word(SC520_PIOCLR31_16, 0x0003);     /* reset SSI chip-selects */
+		write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+
+	} else {
+		/* set up the GP IO pins (for the Hyglo board) */
+		write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); 	/* set the GPIO pin function 31-16 reg */
+		write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f);  	/* set the GPIO pin function 15-0 reg */
+		write_mmcr_word(SC520_PIODIR31_16, 0x003f); 	/* set the GPIO direction 31-16 reg */
+		write_mmcr_word(SC520_PIODIR15_0, 0xe180);  	/* set the GPIO direction 15-0 reg */
+		write_mmcr_byte(SC520_CSPFS, 0x00);  		/* set the CS pin function reg */	
+		write_mmcr_byte(SC520_CLKSEL, 0x70);
+		
+		write_mmcr_word(SC520_PIOCLR15_0, 0x0180);      /* reset SSI chip-selects */
+	}
+	
+	write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */    	
+	write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
+	write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
+	write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
+	write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
+        write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
+	write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
+
+	write_mmcr_word(SC520_BOOTCSCTL, 0x0407);		/* set up timing of BOOTCS */ 
+	
+	/* adjust the memory map:
+	 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
+	 * and 256MB to 1G-128k  (0x1000000 - 0x37ffffff) is mapped to PCI mmio
+	 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */ 
+	
+		
+	
+	/* bootcs */
+	write_mmcr_long(SC520_PAR12, 0x8bffe800);		
+	
+	/* IDE0 = GPCS6 1f0-1f7 */
+	write_mmcr_long(SC520_PAR3,  0x380801f0);		
+
+	/* IDE1 = GPCS7 3f6 */
+	write_mmcr_long(SC520_PAR4,  0x3c0003f6);		
+
+	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */	
+
+	write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));	
+
+}
+
+
+
+/* par usage:
+ * PAR0   (legacy_video)
+ * PAR1   (PCI ROM mapping)
+ * PAR2 
+ * PAR3   IDE 
+ * PAR4   IDE
+ * PAR5   (legacy_video)
+ * PAR6 
+ * PAR7   (legacy_video)
+ * PAR8   (legacy_video)
+ * PAR9   (legacy_video)
+ * PAR10
+ * PAR11  (ISAROM)
+ * PAR12  BOOTCS
+ * PAR13
+ * PAR14
+ * PAR15
+ */
+
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ * 
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size) 
+{
+	u32 par;
+	
+	printf("isa_map_rom asked to map %d bytes at %x\n", 
+	       size, bus_addr);
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+	
+	printf ("setting PAR11 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR11,  par);
+	
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	printf("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
+		write_mmcr_long(SC520_PAR11, 0);
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+}
+
+#ifdef CONFIG_PCI
+#define PCI_ROM_TEMP_SPACE 0x10000
+/* 
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address 
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size) 
+{
+	u32 par;
+	
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+	
+	printf ("setting PAR1 to %x\n", par);
+	
+	/* Map rom 0x10000 with PAR1 */
+	write_mmcr_long(SC520_PAR1,  par);
+	
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	printf("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		write_mmcr_long(SC520_PAR1, 0);
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+	
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus. 
+ * After this function accesses to I/O ports 0x3b0-0x3bb and 
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ * 
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	write_mmcr_long(SC520_PAR0,  0x7200400a);
+	
+	/* forward all I/O accesses to PCI */
+	write_mmcr_byte(SC520_ADDDECCTL, 
+			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);	
+	
+	
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers 
+	 */
+	
+	/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
+	write_mmcr_long(SC520_PAR5, 0x31f70100);		
+		
+	/* com2 use 2f8-2ff */
+	
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	write_mmcr_long(SC520_PAR7, 0x30af0300);		
+	
+	/* vga use 3b0-3bb */
+	
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	write_mmcr_long(SC520_PAR8, 0x300303bc);		
+	
+	/* vga use 3c0-3df */
+	
+	/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
+	write_mmcr_long(SC520_PAR9, 0x301703e0);		
+		
+	/* com1 use 3f8-3ff */		
+
+	return 0;
+}
+#endif
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	
+	init_sc520();	
+	bus_init();
+	irq_init();
+		
+	/* max drive current on SDRAM */
+	write_mmcr_word(SC520_DSCTL, 0x0100);
+		
+	/* enter debug mode after next reset (only if jumper is also set) */
+	write_mmcr_byte(SC520_RESCFG, 0x08);
+	/* configure the software timer to 33.000MHz */
+	write_mmcr_byte(SC520_SWTMRCFG, 1);
+	gd->bus_clk = 33000000;
+	
+	return 0;
+}
+
+int dram_init(void)
+{
+	init_sc520_dram();
+	return 0;
+}
+
+void show_boot_progress(int val)
+{
+ 	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	if (version == 0) {
+		/* PIO31-PIO16 Data */
+		write_mmcr_word(SC520_PIODATA31_16,                                           
+				(read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
+		
+		/* PIO0-PIO15 Data */
+		write_mmcr_word(SC520_PIODATA15_0, 
+				(read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
+	} else {
+		/* newer boards use PIO4-PIO12 */
+		/* PIO0-PIO15 Data */
+#if 0		
+		val = (val & 0x007) | ((val & 0x038) << 3) | ((val & 0x1c0) >> 3); 
+#else
+		val = (val & 0x007) | ((val & 0x07e) << 2); 
+#endif
+		write_mmcr_word(SC520_PIODATA15_0, 
+				(read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
+	}
+}
+
+
+int last_stage_init(void)
+{
+	
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	printf("Omicron Ceti SC520 Spunk revision %x\n", version);
+	
+#if 0
+	if (version) {
+		int x, y;
+		
+		printf("eeprom probe %d\n", spi_eeprom_probe(1));
+		
+		spi_eeprom_read(1, 0, (u8*)&x, 2);
+		spi_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+		x ^= 0xffff;
+		y ^= 0xffff;
+		spi_eeprom_write(1, 0, (u8*)&x, 2);
+		spi_eeprom_write(1, 1, (u8*)&y, 2);
+		
+		spi_eeprom_read(1, 0, (u8*)&x, 2);
+		spi_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+		
+	} else {
+		int x, y;
+		
+		printf("eeprom probe %d\n", mw_eeprom_probe(1));
+		
+		mw_eeprom_read(1, 0, (u8*)&x, 2);
+		mw_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+		
+		x ^= 0xffff;
+		y ^= 0xffff;
+		mw_eeprom_write(1, 0, (u8*)&x, 2);
+		mw_eeprom_write(1, 1, (u8*)&y, 2);
+		
+		mw_eeprom_read(1, 0, (u8*)&x, 2);
+		mw_eeprom_read(1, 1, (u8*)&y, 2);
+		printf("eeprom bytes %04x%04x\n", x, y);
+		
+		
+	}
+#endif
+
+	ds1722_probe(2);
+	
+	return 0;
+}
+
+void ssi_chip_select(int dev) 
+{
+	int version = read_mmcr_byte(SC520_SYSINFO);
+	
+	if (version) {
+		/* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
+		switch (dev) {
+		case 1: /* EEPROM */
+			write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
+			break;
+			
+		case 2: /* Temp Probe */
+			write_mmcr_word(SC520_PIOSET31_16, 0x0002);
+			break;
+			
+		case 3: /* CAN */
+			write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
+			break;
+			
+		case 4: /* AUX */				
+			write_mmcr_word(SC520_PIOSET31_16, 0x0001);
+			break;
+		
+		case 0:
+			write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
+			write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+			break;
+			
+		default:
+			printf("Illegal SSI device requested: %d\n", dev);
+		}
+	} else {
+		
+		/* Globox board: Both EEPROM and TEMP are active-high */
+
+		switch (dev) {
+		case 1: /* EEPROM */
+			write_mmcr_word(SC520_PIOSET15_0, 0x0100);
+			break;
+			
+		case 2: /* Temp Probe */
+			write_mmcr_word(SC520_PIOSET15_0, 0x0080);
+			break;
+		
+		case 0:
+			write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
+			break;
+			
+		default:
+			printf("Illegal SSI device requested: %d\n", dev);
+		}
+	}	
+}
+
+
+void spi_init_f(void) 
+{
+	read_mmcr_byte(SC520_SYSINFO) ?
+		spi_eeprom_probe(1) : 
+	mw_eeprom_probe(1);
+	
+}
+
+ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) 
+{
+	int offset;
+	int i;
+	
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+	
+	return 	read_mmcr_byte(SC520_SYSINFO) ?
+		spi_eeprom_read(1, offset, buffer, len) : 
+	mw_eeprom_read(1, offset, buffer, len);
+}
+
+ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) 
+{
+	int offset;
+	int i;
+	
+	offset = 0;
+	for (i=0;i<alen;i++) {
+		offset <<= 8;
+		offset |= addr[i];
+	}
+	
+	return 	read_mmcr_byte(SC520_SYSINFO) ?
+		spi_eeprom_write(1, offset, buffer, len) : 
+	mw_eeprom_write(1, offset, buffer, len);
+}
+
diff --git a/board/sc520_spunk/sc520_spunk_asm.S b/board/sc520_spunk/sc520_spunk_asm.S
new file mode 100644
index 00000000000..e198125b8c8
--- /dev/null
+++ b/board/sc520_spunk/sc520_spunk_asm.S
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* now setup the General purpose bus to give us access to the LEDs.
+ * We can then use the leds to display status information.
+ */ 
+
+sc520_cdp_registers:
+/* size    offset        value */
+.word 1 ; .word 0x040 ; .long 0x00       /* SDRAM buffer control */
+.word 2 ; .word 0xc08 ; .long 0x0001     /* GP CS offset */
+.word 2 ; .word 0xc09 ; .long 0x0003     /* GP CS width */
+.word 2 ; .word 0xc0a ; .long 0x0001     /* GP CS width */
+.word 2 ; .word 0xc0b ; .long 0x0003     /* GP RD pulse width */
+.word 2 ; .word 0xc0c ; .long 0x0001     /* GP RD offse */
+.word 2 ; .word 0xc0d ; .long 0x0003     /* GP WR pulse width */
+.word 2 ; .word 0xc0e ; .long 0x0001     /* GP WR offset */
+.word 2 ; .word 0xc2c ; .long 0x003f     /* GPIO directionreg 31-16 */
+.word 2 ; .word 0xc2a ; .long 0xe000     /* GPIO directionreg 15-0 */
+.word 2 ; .word 0xc22 ; .long 0xffc0     /* GPIO pin function 31-16 reg */
+.word 2 ; .word 0xc20 ; .long 0x1fff     /* GPIO pin function 15-0 reg */
+.word 0 ; .word 0x000 ; .long 0x00
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+        movl    $sc520_cdp_registers,%esi
+init_loop:	
+        movl    $0xfffef000,%edi     /* MMCR base to edi */					
+	movw	(%esi), %bx          /* load size to bx */
+	cmpw	$0, %bx              /* if size is 0 we're done */
+	je	done 
+	xorl	%edx,%edx
+	movw	2(%esi), %dx        /* load MMCR offset to dx */
+	addl	%edx, %edi          /* add offset to base in edi */
+	movl	4(%esi), %eax       /* load value in eax */
+	cmpw	$1, %bx
+	je	byte                 /* byte op? */
+	cmpw	$2, %bx
+	je	word                 /* word op? */
+	movl	%eax, (%edi)         /* must be long, then */
+	jmp	next
+byte:   movb    %al,(%edi)        
+	jmp	next
+word:	movw	%ax,(%edi)
+next:	addl	$8, %esi             /* advance esi */
+	jmp	init_loop
+
+	/* light all leds */
+done:   movl    $0xfffefc32,%edx 
+	movw    $0000,(%edx)              
+
+	jmp 	*%ebp		     /* return to caller */
+
+
+.globl __show_boot_progress
+__show_boot_progress:
+	movl    $0xfffefc32,%edx 
+	xorw    $0xffff, %ax 
+	movw    %ax,(%edx)              
+	jmp	*%ebp
+
diff --git a/board/sc520_spunk/sc520_spunk_asm16.S b/board/sc520_spunk/sc520_spunk_asm16.S
new file mode 100644
index 00000000000..cdcbbbef6a7
--- /dev/null
+++ b/board/sc520_spunk/sc520_spunk_asm16.S
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 16bit initialization code.
+ * This code have to map the area of the boot flash
+ * that is used by U-boot to its final destination.
+ */
+
+.text
+.section .start16, "ax"
+.code16
+.globl board_init16
+board_init16:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax	
+	outl	%eax, %dx		
+	
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax		
+	movw	%ax, %ds		 
+		
+	/* Map the entire flash at 0x38000000  
+	 * (with BOOTCS and PAR14, use 0xabfff800 for ROMCS1) */
+	movl    $0xc0, %edi
+        movl	$0x8bfff800, %eax
+        movl	%eax, (%di)		
+
+	/* Disable SDRAM write buffer */
+	movw    $0x40,%di
+        xorw    %ax,%ax
+        movb    %al, (%di)              
+
+	/* Disabe MMCR alias */
+	movw	$0xfffc, %dx
+	movl	$0x000000cb, %eax	
+	outl	%eax, %dx		
+	
+	/* the return address is stored in bp */
+	jmp	*%bp
+	
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+realmode_reset:
+	/* Alias MMCR to 0xdf000 */
+	movw	$0xfffc, %dx
+	movl	$0x800df0cb, %eax	
+	outl	%eax, %dx		
+	
+	/* Set ds to point to MMCR alias */
+	movw	$0xdf00, %ax		
+	movw	%ax, %ds		 
+		
+	/* issue software reset thorugh MMCR */
+	movl    $0xd72, %edi
+        movb	$0x01, %al
+        movb	%al, (%di)		
+
+1:	hlt
+	jmp	1
+	
diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds
new file mode 100644
index 00000000000..fbab9b85f25
--- /dev/null
+++ b/board/sc520_spunk/u-boot.lds
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{	
+	. = 0x387c0000;                     /* Where bootcode in the flash is mapped */
+	.text  : { *(.text); }
+	
+        . = ALIGN(4);
+        .rodata : { *(.rodata) }
+
+        . = 0x400000; 	                    /* Ram data segment to use */
+	_i386boot_romdata_dest = ABSOLUTE(.);
+        .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
+	_i386boot_romdata_start = LOADADDR(.data); 	
+
+        . = ALIGN(4);
+        .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
+	_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got); 	
+
+
+        . = ALIGN(4);
+	_i386boot_bss_start = ABSOLUTE(.);
+        .bss : { *(.bss) }	
+	_i386boot_bss_size = SIZEOF(.bss);
+	
+	
+	/* 16bit realmode trampoline code */
+	.realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) }
+    
+	_i386boot_realmode = LOADADDR(.realmode);
+	_i386boot_realmode_size = SIZEOF(.realmode);
+	
+	/* 16bit BIOS emulation code (just enough to boot Linux) */
+	.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
+    
+	_i386boot_bios = LOADADDR(.bios);
+	_i386boot_bios_size = SIZEOF(.bios);
+	
+
+	/* The load addresses below assumes that the flash
+	 * will be mapped so that 0x387f0000 == 0xffff0000
+	 * at reset time
+	 *
+	 * The fe00 and ff00 offsets of the start32 and start16 
+	 * segments are arbitrary, the just have to be mapped
+	 * at reset and the code have to fit.
+	 * The fff0 offset of reset is important, however.
+	 */
+	 
+	 
+	. = 0xfffffe00;
+	.start32 : AT (0x387ffe00) { *(.start32); } 
+	
+	. = 0xff00;
+	.start16 : AT (0x387fff00) { *(.start16); }  
+	
+	. = 0xfff0;
+	.reset : AT (0x387ffff0) { *(.reset); }  
+	_i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
+}