diff options
| author | Peter Tyser <ptyser@xes-inc.com> | 2009-02-05 11:25:25 -0600 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2009-02-16 18:05:56 -0600 |
| commit | 4ef630df773e45806d701bf5d25c328778bb4cde (patch) | |
| tree | 2abadc50a689dc639f319f8dcb2e29b5bb55d6e1 /board/sbc8641d | |
| parent | edf0e2524a8c6a3e91c009c496a0aa0ae89cd8ab (diff) | |
86xx: Reset update
Update the 86xx reset sequence to try executing a board-specific reset
function. If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'board/sbc8641d')
| -rw-r--r-- | board/sbc8641d/sbc8641d.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 508bdc5dd82..52ad2d86c9d 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -384,3 +384,32 @@ unsigned long get_board_sys_clk (ulong dummy) return val; } + +void board_reset(void) +{ +#ifdef CONFIG_SYS_RESET_ADDRESS + ulong addr = CONFIG_SYS_RESET_ADDRESS; + + /* flush and disable I/D cache */ + __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); + __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); + __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); + __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 4"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("mtspr 1008, 5"); + __asm__ __volatile__ ("isync"); + __asm__ __volatile__ ("sync"); + + /* + * SRR0 has system reset vector, SRR1 has default MSR value + * rfi restores MSR from SRR1 and sets the PC to the SRR0 value + */ + __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); + __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); + __asm__ __volatile__ ("mtspr 27, 4"); + __asm__ __volatile__ ("rfi"); +#endif +} |