diff options
| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2011-12-30 23:53:08 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-01-11 13:58:14 -0600 |
| commit | f0aec4ea3301f7db3a691ec0cbb5230e99cceb34 (patch) | |
| tree | ff563f7ef8c292f077d1009917d296fc0e82ade8 /board/sbc8548 | |
| parent | 3fd673cf363bc86ed42eff713d4e3506720e91a2 (diff) | |
sbc8548: enable ability to boot from alternate flash
This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module. Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6. This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.
To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.
We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.
The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/sbc8548')
| -rw-r--r-- | board/sbc8548/law.c | 8 | ||||
| -rw-r--r-- | board/sbc8548/sbc8548.c | 2 | ||||
| -rw-r--r-- | board/sbc8548/tlb.c | 19 |
3 files changed, 28 insertions, 1 deletions
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index febb6829c35..c263191c3dd 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -41,13 +41,21 @@ * 0xf8b0_0000 0xf80f_ffff EEPROM 1M * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M * + * If swapped CS0/CS6 via JP12+SW2.8: + * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. */ struct law_entry law_table[] = { +#ifdef CONFIG_SYS_ALT_BOOT + SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC), +#else SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#endif #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 26095a54559..63d504d61da 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -113,7 +113,7 @@ void lbc_sdram_init(void) puts(" SDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index e9cedc7c0dc..4bf72147bad 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -104,6 +104,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_16M, 1), +#ifndef CONFIG_SYS_ALT_BOOT /* * TLB 6: 64M Non-cacheable, guarded * 0xec000000 64M 64MB user FLASH @@ -111,6 +112,24 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), +#else + /* + * TLB 6: 4M Non-cacheable, guarded + * 0xef800000 4M 1st 1/2 8MB soldered FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_4M, 1), + + /* + * TLB 7: 4M Non-cacheable, guarded + * 0xefc00000 4M 2nd half 8MB soldered FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, + CONFIG_SYS_ALT_FLASH + 0x400000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_4M, 1), +#endif }; |