diff options
| author | Niklaus Giger <niklaus.giger@member.fsf.org> | 2009-10-04 20:04:20 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-07 09:15:20 +0200 |
| commit | ddc922ff2c20ae0b7f9ce2df1ac28143e2f325bd (patch) | |
| tree | 5c390395480e4cfd575ef751edd34034eaffa142 /board/sandburst | |
| parent | f80e61dcfe53fa3a5936659883415c9bd1b5a3d9 (diff) | |
ppc_4xx: Apply new HW register names
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/sandburst')
| -rw-r--r-- | board/sandburst/common/ppc440gx_i2c.h | 2 | ||||
| -rw-r--r-- | board/sandburst/common/sb_common.c | 22 |
2 files changed, 12 insertions, 12 deletions
diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h index 328abd64b89..90f27caa0da 100644 --- a/board/sandburst/common/ppc440gx_i2c.h +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -44,7 +44,7 @@ #define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS) #define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR) #define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR) -#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV) +#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IIC0_CLKDIV) #define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK) #define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT) #define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS) diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index e1c61463dd2..a484874ea35 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -346,28 +346,28 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_BAR0, 0 ); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ |