summaryrefslogtreecommitdiff
path: root/board/renesas
diff options
context:
space:
mode:
authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2014-10-31 16:08:11 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2014-11-04 08:58:23 +0900
commitd8659c6d25219e3f89b6696b86c3b18dcf5c3fb5 (patch)
tree68612b75bf9eee938b4c496cb2d5ba66502251f0 /board/renesas
parent3372a9a7a83ca62f5d3536afef8aec6ac553ad9e (diff)
arm: rmobile: lager: Fix change of the CPU frequency
The change of the CPU frequency is waited for until PLL0ST of the PLLECR is set to 1. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas')
-rw-r--r--board/renesas/lager/lager.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 5302839b33a..1fc5833ebeb 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -36,9 +36,14 @@ void s_init(void)
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
+ u32 stat = 0;
u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
<< PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+ do {
+ stat = readl(PLLECR) & PLL0ST;
+ } while (stat == 0x0);
}
/* QoS(Quality-of-Service) Init */