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| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2019-03-30 07:05:09 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-03-30 07:31:02 +0100 |
| commit | 4bbd464268f4c70d9704d41d10b5d324b6dc4549 (patch) | |
| tree | 1ceb013dc205c352fc1c1abe5c2bc998a6ffd10c /board/renesas/lager/lager.c | |
| parent | 573b0f244c16f3f80441932f25fb64e77a7a6c31 (diff) | |
ARM: rmobile: Fix PHY LED mode register mask
The PHY LED mode register mask should be 0xc000 , not 0xc0000.
Correct the mask to operate on the right bits.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/renesas/lager/lager.c')
| -rw-r--r-- | board/renesas/lager/lager.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 062e88c198..f062bb0172 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -109,7 +109,7 @@ int dram_init_banksize(void) /* KSZ8041NL/RNL */ #define PHY_CONTROL1 0x1E -#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE 0xC000 #define PHY_LED_MODE_ACK 0x4000 int board_phy_config(struct phy_device *phydev) { |