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authorwdenk <wdenk>2004-06-19 21:19:10 +0000
committerwdenk <wdenk>2004-06-19 21:19:10 +0000
commit49822e23a09e2f529e6774ad61f23e43ab208cbc (patch)
treed6cbe0c141f10778b944fddbfc473a91d4bea7c0 /board/pm520/mt48lc16m16a2-75.h
parent46a414dc12c7809ac3c3e82b6198a1f435d7489f (diff)
Patch by Josef Wagner, 04 Jun 2004:
- DDR Ram support for PM520 (MPC5200) - support for different flash types (PM520) - USB / IDE / CF-Card / DiskOnChip support for PM520 - 8 bit boot rom support for PM520/CE520 - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) - I2C and RTC support for CPC45 - support of new flash type (28F160C3T) for CPC45
Diffstat (limited to 'board/pm520/mt48lc16m16a2-75.h')
-rw-r--r--board/pm520/mt48lc16m16a2-75.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h
new file mode 100644
index 0000000000..ffdf0396a5
--- /dev/null
+++ b/board/pm520/mt48lc16m16a2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE 0x008D0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xC2222600
+#define SDRAM_CONFIG2 0x88B70004
+#define SDRAM_ADDRSEL 0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif