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authorStefan Roese <sr@denx.de>2008-01-30 15:35:50 +0100
committerStefan Roese <sr@denx.de>2008-02-04 11:47:40 +0100
commite1d1429b49b0ee58c80f8c7b29c1ebaf8be7f5f1 (patch)
treeec68ac6e1f31bedb30d63d7a124cdf788eee89d4 /board/pcs440ep
parent28d77d968bfe0316deb5bf15c17f57d5ff2c8821 (diff)
ppc4xx: Fix GPIO configuration for pcs440ep
The SRD0_PFC0 register was not configured correctly to enable the GPIO's 49-63 for GPIO. They have been configured as trace signals. This patch fixes this by clearing the corresponding bit. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/pcs440ep')
-rw-r--r--board/pcs440ep/pcs440ep.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 90e99d3dca8..96adbc915d3 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -175,7 +175,7 @@ int board_early_init_f(void)
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
- mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */
+ mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
return 0;