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authorwdenk <wdenk>2004-02-23 22:22:28 +0000
committerwdenk <wdenk>2004-02-23 22:22:28 +0000
commit63e73c9a8ed5b32d9c4067ffaad953e9a8fe8f0a (patch)
tree2f8915e0b3024c639748e930b56d60c0d8cf2d99 /board/omap1610inn/platform.S
parentcd0a9de68b03e5a54fd2a08f44be318e4397be01 (diff)
* Patches by Reinhard Meyer, 14 Feb 2004:
- update board/emk tree; use common flash driver - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c [adapted for other PPC CPUs -- wd] - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c * Patch by Jon Diekema, 13 Feb 2004: Call show_boot_progress() whenever POST "FAILED" is printed. * Patch by Nishant Kamat, 13 Feb 2004: Add support for TI OMAP1610 H2 Board Fixes for cpu/arm926ejs/interrupt.c (based on Richard Woodruff's patch for arm925, 16 Oct 03) Fix for a timer bug in OMAP1610 Innovator Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2 * Patches by Stephan Linz, 12 Feb 2004: - add support for NIOS timer with variable period preload counter value - prepare POST framework support for NIOS targets * Patch by Denis Peter, 11 Feb 2004: add POST support for the MIP405 board
Diffstat (limited to 'board/omap1610inn/platform.S')
-rw-r--r--board/omap1610inn/platform.S49
1 files changed, 49 insertions, 0 deletions
diff --git a/board/omap1610inn/platform.S b/board/omap1610inn/platform.S
index cad152b7b25..17756953ead 100644
--- a/board/omap1610inn/platform.S
+++ b/board/omap1610inn/platform.S
@@ -5,6 +5,8 @@
* Texas Instruments, <www.ti.com>
* Kshitij Gupta <Kshitij@ti.com>
*
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -248,6 +250,22 @@ common_tc:
ldr r1, VAL_TC_EMIFS_CS3_CONFIG
ldr r0, REG_TC_EMIFS_CS3_CONFIG
str r1, [r0] /* Chip Select 3 */
+
+#ifdef CONFIG_H2_OMAP1610
+ /* inserting additional 2 clock cycle hold time for LAN */
+ ldr r0, REG_TC_EMIFS_CS1_ADVANCED
+ ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
+ str r1, [r0]
+#endif
+ /* Start MPU Timer 1 */
+ ldr r0, REG_MPU_LOAD_TIMER
+ ldr r1, VAL_MPU_LOAD_TIMER
+ str r1, [r0]
+
+ ldr r0, REG_MPU_CNTL_TIMER
+ ldr r1, VAL_MPU_CNTL_TIMER
+ str r1, [r0]
+
/* back to arch calling code */
mov pc, lr
@@ -266,6 +284,11 @@ REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
.word 0xfffecc1c
+#ifdef CONFIG_H2_OMAP1610
+REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
+ .word 0xfffecc54
+#endif
+
/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL: /* 16 bits */
.word 0xfffece00
@@ -338,6 +361,11 @@ REG_DLL_LRD_CONTROL:
REG_WATCHDOG:
.word 0xfffec808
+REG_MPU_LOAD_TIMER:
+ .word 0xfffec600
+REG_MPU_CNTL_TIMER:
+ .word 0xfffec500
+
/* 96 MHz Samsung Mobile DDR */
SDRAM_CONFIG_VAL:
.word 0x001200f4
@@ -350,6 +378,7 @@ VAL_ARM_CKCTL:
VAL_DPLL1_CTL:
.word 0x2830
+#ifdef CONFIG_INNOVATOROMAP1610
VAL_TC_EMIFS_CS0_CONFIG:
.word 0x002130b0
VAL_TC_EMIFS_CS1_CONFIG:
@@ -358,6 +387,21 @@ VAL_TC_EMIFS_CS2_CONFIG:
.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
.word 0x88011131
+#endif
+
+#ifdef CONFIG_H2_OMAP1610
+VAL_TC_EMIFS_CS0_CONFIG:
+ .word 0x00203331
+VAL_TC_EMIFS_CS1_CONFIG:
+ .word 0x8180fff3
+VAL_TC_EMIFS_CS2_CONFIG:
+ .word 0xf800f22a
+VAL_TC_EMIFS_CS3_CONFIG:
+ .word 0x88011131
+VAL_TC_EMIFS_CS1_ADVANCED:
+ .word 0x00000022
+#endif
+
VAL_TC_EMIFF_SDRAM_CONFIG:
.word 0x010290fc
VAL_TC_EMIFF_MRS:
@@ -376,6 +420,11 @@ WATCHDOG_VAL1:
WATCHDOG_VAL2:
.word 0x000000a0
+VAL_MPU_LOAD_TIMER:
+ .word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+ .word 0xffffffa1
+
/* command values */
.equ CMD_SDRAM_NOP, 0x00000000
.equ CMD_SDRAM_PRECHARGE, 0x00000001