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authorTom Warren <twarren.nvidia@gmail.com>2013-02-08 07:25:31 +0000
committerTom Warren <twarren@nvidia.com>2013-03-14 11:06:41 -0700
commitb77c3547e867f7876b3f970125c45d556588d9cb (patch)
tree1d4bc63e6940d611cd965410f16c6ae0b892f68a /board/nvidia
parente32624ef820f821b94333402788e79979681eb29 (diff)
Tegra114: fdt: Update DT files with I2C info for T114/Dalmore
T114, like T30, does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but I2C5 is used to designate the controller intended for power control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'board/nvidia')
-rw-r--r--board/nvidia/dts/tegra114-dalmore.dts25
1 files changed, 25 insertions, 0 deletions
diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts
index 731557798e7..ed3c2fde286 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -10,4 +10,29 @@
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
+
+ i2c@7000c000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c700 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
};