CHROMIUM: harmony: Very basic harmony (AKA dev-board) support.

Previously, we had dev-board as a symlink to seaboard,
which was a terrible idea (AKA: it wouldn't work at all).
Now, I've made a copy of it and made a few small changes,
mostly making sure that the nand WP pin is right and taking
the keyboard out.

I won't say that it's pretty, but it's better than what was
there.

Lots of TODOs, including trying to resolve this with the DTS
file in ../harmony and actually trying to set these values
to something sane.

This is part of a batch of CLs:
- http://gerrit.chromium.org/gerrit/7838
  Hack it so that bundle_firmware forces one copy of the BCT for NAND.
- http://gerrit.chromium.org/gerrit/5207
  CHROMIUM: cbootimage: Add Bctcopy parameter
- http://gerrit.chromium.org/gerrit/7841
  Revert "Hack tegra2_dev-board to think NAND block size is 64K."
- http://gerrit.chromium.org/gerrit/7837
  Add some very basic NAND support to cros_write_firmware.
- http://gerrit.chromium.org/gerrit/7840
  CHROMIUM: harmony: Very basic harmony (AKA dev-board) support.

BUG=chromium-os:17465
TEST=Used cros_write_firmware to flash u-boot to NAND; rebooted and
saw new u-boot

Change-Id: Ie8e1a8c1bb600e48158bccfd4be226f12a41d3c4
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: http://gerrit.chromium.org/gerrit/7840

1 files changed, 192 insertions, 1 deletions

diff --git a/board/nvidia/seaboard/tegra2-dev-board.dts b/board/nvidia/seaboard/tegra2-dev-board.dts
index ec4ba16fbb..9e54454393 120000..100644
--- a/board/nvidia/seaboard/tegra2-dev-board.dts
+++ b/board/nvidia/seaboard/tegra2-dev-board.dts
@@ -1 +1,192 @@
-tegra2-seaboard.dts
\ No newline at end of file
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ "tegra250.dtsi"
+/include/ "chromeos.dtsi"
+/include/ "flashmap-twostop-2mb.dtsi"
+
+/* WARNING
+ * WARNING
+ * WARNING
+ *
+ * This file is mostly just a copy of the seaboard file and
+ * hasn't been fully vetted.  It does let you get to the
+ * u-boot prompt, but needs lots of love.  It should also
+ * be reconciled against ../harmony/tegra2-harmony.dts (and
+ * we should decide which of these two to delete).
+ *
+ * WARNING
+ * WARNING
+ * WARNING
+ */
+
+/ {
+	model = "NVIDIA Harmony";
+	compatible = "nvidia,harmony", "nvidia,tegra250";
+
+	config {
+		odmdata = <0x300d8011>;
+		hwid = "ARM HARMONY TEST 2428";
+		machine-arch-id = <2731>;
+
+		/* Chrome OS specific GPIO */
+		/*
+		 * Parameter 3 bits
+		 * bit 0: 1=output, 0=input
+		 * bit 1: 1=high, 0=low
+		 * bit 2: 1=active low, 0=active high
+		 */
+		/*write-protect-switch	= <&gpio 23 0>;*/
+		recovery-switch		= <&gpio 56 4>;
+		developer-switch	= <&gpio 168 0>;
+		/*lid-switch		= <&gpio 23 4>;*/
+		power-switch		= <&gpio 170 4>;
+	};
+
+	aliases {
+		console = "/serial@70006300";
+                usb0 = "/usb@0xc5008000";
+                usb1 = "/usb@0xc5000000";
+
+		sdmmc0 = "/sdhci@c8000600";
+		sdmmc1 = "/sdhci@c8000200";
+
+		i2c0 = "/i2c@0x7000d000";
+		i2c1 = "/i2c@0x7000c000";
+		i2c2 = "/i2c@0x7000c400";
+		i2c3 = "/i2c@0x7000c500";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	serial@70006300 {
+		status = "ok";
+		clock-frequency = <216000000>;
+	};
+
+	/*
+	 * TODO(dianders): Don't think harmony has a switch here, but things
+	 * don't boot without this section.  Someone interested in harmony
+	 * should debug the problem.
+	 */
+	switch {
+		compatible = "nvidia,spi-uart-switch";
+		uart = <&uart3>;
+
+		/* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
+		gpios = <&gpio 67 1>; /* Port I = 8 bit = 3: 8 * 8 + 3 */
+	};
+
+	sdhci@c8000200 {
+		status = "ok";
+		width = <4>;	/* width of SDIO port */
+		removable = <1>;
+		/* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
+		cd-gpio = <&gpio 69 0>; /* card detect, gpio PI5 */
+		wp-gpio = <&gpio 57 0>; /* write protect, gpio PH1 */
+		power-gpio = <&gpio 70 3>; /* power enable, gpio PI6 */
+	};
+
+	emmc: sdhci@c8000600 {
+		status = "ok";
+		width = <4>;	/* width of SDIO port */
+		removable = <0>;
+	};
+
+	/*
+	 * TODO(dianders): We don't have a LCD, but we need this section so that
+	 * we don't hang at boot (theory is that the problem is that the default
+	 * environment says to print to the LCD).
+	 */
+	lcd {
+		compatible = "nvidia,tegra2-lcd";
+		width = <1366>;
+		height = <768>;
+		bits_per_pixel = <16>;
+		pwfm = <&pwfm2>;
+		display = <&display1>;
+		frame-buffer = <0x37680000>;
+
+		pixel_clock = <70600000>;
+
+		/* Timing: ref_to_sync, sync_width. back_porch, front_porch */
+		horiz_timing = <11 58 58 58>;
+		vert_timing = <1 4 4 4>;
+
+		/* Parameter 3 bit 0:1=output, 0=input; bit 1:1=high, 0=low */
+		backlight-enable = <&gpio 28 1>;	/* PD4 */
+		lvds-shutdown = <&gpio 10 1>;		/* PB2 */
+		backlight-vdd = <&gpio 176 1>;		/* PW0 */
+		panel-vdd = <&gpio 22 1>;		/* PC6 */
+
+		/*
+		 * Panel required timings
+		 * Timing 1: delay between panel_vdd-rise and data-rise
+		 * Timing 2: delay between data-rise and backlight_vdd-rise
+		 * Timing 3: delay between backlight_vdd and pwm-rise
+		 * Timing 4: delay between pwm-rise and backlight_en-rise
+		 */
+		panel-timings = <4 203 17 15>;
+	};
+
+	usb@0xc5000000 {
+		status = "ok";
+		host-mode = <1>;
+	};
+
+	usbphy: usbphy@0 {
+		compatible = "smsc,usb3315";
+		status = "ok";
+	};
+
+	usb@0xc5008000 {
+		status = "ok";
+		utmi = <&usbphy>;
+		host-mode = <0>;
+	};
+
+	flash@0x70008000 {
+		compatible = "hynix,HY27UF4G2B", "nand-flash";
+		controller = <&nand>;
+
+		/* How many bytes for data area */
+		page-data-bytes = <2048>;
+
+		/* How many ECC bytes to be generated for tag bytes */
+		tag-ecc-bytes = <4>;
+
+		/* How many tag bytes in spare area */
+		tag-bytes = <20>;
+
+		/* How many ECC bytes for data area */
+		data-ecc-bytes = <36>;
+
+		skipped-spare-bytes = <4>;
+
+		/*
+		 * How many bytes in spare area
+		 * spare area = skipped bytes + ECC bytes of data area
+		 * + tag bytes + ECC bytes of tag bytes
+		 */
+		page-spare-bytes = <64>;
+
+		/*
+		 * MAX_TRP_TREA:
+		 * non-EDO mode: value (in ns) = Max(tRP, tREA) + 6ns
+		 * EDO mode: value (in ns) = tRP timing
+		 *
+		 * Timing values: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
+		 *	TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
+		 */
+		timing = <26 100 20 80 20 10 12 10 70>;
+	};
+
+	nand-controller@0x70008000 {
+		status = "ok";
+		wp-gpio = <&gpio 23 3>;		/* PC7 */
+		width = <8>;
+	};
+};