CHROMIUM: decode GPIO configs through <&gpio ...>

cros_gpio module used a ad-hoc format of GPIO config, and it should
use <&gpio ...> instead. This patch changes the format of GPIO config.

Note: In between calls to gpio_direction_input() (in fdt_setup_gpio())
and calls to gpio_get_value(), you have to insert a small delay if the
input source is connected to the GPIO through a sufficiently large
series resister (say, 200K ohm) so that the RC time constant for
charging the gate capacitance on the input is non-trivial.

As a matter of fact, I tested on Kaen and Aebl, and found only write
protect GPIO needs this delay, and the delay time is less than 10 us.
And we may safely hide this delay by decoupling the initialization and
reading of GPIOs.

BUG=none
TEST=Run "vboot_test gpio" on Kaen and Aebl, and check GPIO readings
TEST=Run "crossystem" on Kaen and Aebl after boot, and check GPIO readings

Change-Id: Ib4d93c2ce156eb09ffc24a3882f83490d25c1e91
Reviewed-on: http://gerrit.chromium.org/gerrit/5726
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>

6 files changed, 114 insertions, 90 deletions

diff --git a/board/nvidia/chromeos/cros_gpio.c b/board/nvidia/chromeos/cros_gpio.c
index 10c8a40994c..ad5813fb71c 100644
--- a/board/nvidia/chromeos/cros_gpio.c
+++ b/board/nvidia/chromeos/cros_gpio.c
@@ -22,47 +22,74 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int cros_gpio_fetch(enum cros_gpio_index index, cros_gpio_t *gpio)
+static char *gpio_name[CROS_GPIO_MAX_GPIO] = {
+	"write-protect-switch",
+	"recovery-switch",
+	"developer-switch",
+	"lid-switch",
+	"power-switch",
+};
+
+static int g_config_node = -1;
+static unsigned long g_valid_time;
+
+int misc_init_r(void)
 {
-	const char const *port[CROS_GPIO_MAX_GPIO] = {
-		"gpio_port_write_protect_switch",
-		"gpio_port_recovery_switch",
-		"gpio_port_developer_switch",
-		"gpio_port_lid_switch",
-		"gpio_port_power_switch",
-	};
-	const char const *polarity[CROS_GPIO_MAX_GPIO] = {
-		"polarity_write_protect_switch",
-		"polarity_recovery_switch",
-		"polarity_developer_switch",
-		"polarity_lid_switch",
-		"polarity_power_switch",
-	};
-	int p;
+	struct fdt_gpio_state gs;
+	int i, config_node;
 
-	if (index < 0 || index >= CROS_GPIO_MAX_GPIO) {
-		VBDEBUG(PREFIX "index out of range: %d\n", index);
+	config_node = fdt_path_offset(gd->blob, "/config");
+	if (config_node < 0)
 		return -1;
+
+	for (i = 0; i < CROS_GPIO_MAX_GPIO; i++) {
+		if (fdt_decode_gpio(gd->blob, config_node, gpio_name[i], &gs))
+			return -1;
+		fdt_setup_gpio(&gs);
 	}
 
-	gpio->index = index;
+	/*
+	 * In theory we have to insert a delay here for charging the input
+	 * gate capacitance. Consider a 200K ohms series resister and 10
+	 * picofarads gate capacitance.
+	 *
+	 * RC time constant is
+	 *     200 K ohms * 10 picofarads = 2 microseconds
+	 *
+	 * Then 10-90% rise time is
+	 *     2 microseconds * 2.2 = 4.4 microseconds
+	 *
+	 * Thus, 10 microseconds gives us a 50% margin.
+	 */
+	g_valid_time = timer_get_us() + 10;
+	g_config_node = config_node;
 
-	gpio->port = fdt_decode_get_config_int(gd->blob, port[index], -1);
-	if (gpio->port == -1) {
-		VBDEBUG(PREFIX "failed to decode gpio port\n");
-		return -1;
-	}
+	return 0;
+}
+
+int cros_gpio_fetch(enum cros_gpio_index index, cros_gpio_t *gpio)
+{
+	struct fdt_gpio_state gs;
+	int p;
 
-	gpio_direction_input(gpio->port);
+	assert(g_config_node >= 0);
+	assert(index >= 0 && index < CROS_GPIO_MAX_GPIO);
 
-	gpio->polarity =
-		fdt_decode_get_config_int(gd->blob, polarity[index], -1);
-	if (gpio->polarity == -1) {
-		VBDEBUG(PREFIX "failed to decode gpio polarity\n");
+	if (fdt_decode_gpio(gd->blob, g_config_node, gpio_name[index], &gs)) {
+		VBDEBUG(PREFIX "fail to decode gpio: %d\n", index);
 		return -1;
 	}
 
+	gpio->index = index;
+	gpio->port = gs.gpio;
+	gpio->polarity = (gs.flags & FDT_GPIO_ACTIVE_LOW) ?
+		CROS_GPIO_ACTIVE_LOW : CROS_GPIO_ACTIVE_HIGH;
 	p = (gpio->polarity == CROS_GPIO_ACTIVE_HIGH) ? 0 : 1;
+
+	/* We can only read GPIO after g_valid_time */
+	while (timer_get_us() < g_valid_time)
+		udelay(10);
+
 	gpio->value = p ^ gpio_get_value(gpio->port);
 
 	return 0;
diff --git a/board/nvidia/seaboard/tegra2-aebl.dts b/board/nvidia/seaboard/tegra2-aebl.dts
index 168da7eac76..d7b72fc4971 100644
--- a/board/nvidia/seaboard/tegra2-aebl.dts
+++ b/board/nvidia/seaboard/tegra2-aebl.dts
@@ -14,19 +14,18 @@
 		hwid = "ARM AEBL TEST 5789";
 		machine-arch-id = <3287>;
 
-		/* Chrome OS specific GPIO port number */
-		gpio_port_write_protect_switch	= <59>;
-		gpio_port_recovery_switch	= <56>;
-		gpio_port_developer_switch	= <168>;
-		gpio_port_lid_switch		= <23>;
-		gpio_port_power_switch		= <170>;
-
-		/* GPIO polarity: 0=active_low, 1=active_high */
-		polarity_write_protect_switch	= <0>;
-		polarity_recovery_switch	= <0>;
-		polarity_developer_switch	= <1>;
-		polarity_lid_switch		= <0>;
-		polarity_power_switch		= <0>;
+		/* Chrome OS specific GPIO */
+		/*
+		 * Parameter 3 bits
+		 * bit 0: 1=output, 0=input
+		 * bit 1: 1=high, 0=low
+		 * bit 2: 1=active low, 0=active high
+		 */
+		write-protect-switch	= <&gpio 59 4>;
+		recovery-switch		= <&gpio 56 4>;
+		developer-switch	= <&gpio 168 0>;
+		lid-switch		= <&gpio 23 4>;
+		power-switch		= <&gpio 170 4>;
 	};
 
 	aliases {
diff --git a/board/nvidia/seaboard/tegra2-arthur.dts b/board/nvidia/seaboard/tegra2-arthur.dts
index 8e9edc14457..de598b39b78 100644
--- a/board/nvidia/seaboard/tegra2-arthur.dts
+++ b/board/nvidia/seaboard/tegra2-arthur.dts
@@ -14,19 +14,18 @@
 		hwid = "ARM ARTHUR TEST 3403";
 		machine-arch-id = <3474>;
 
-		/* Chrome OS specific GPIO port number */
-		gpio_port_write_protect_switch	= <59>; /* GMI_AD11 - PH3 */
-		gpio_port_recovery_switch	= <56>; /* GMI_AD08 - PH0 */
-		gpio_port_developer_switch	= <168>; /* GPIO_PV0 - PV0 */
-		gpio_port_lid_switch		= <23>; /* GPIO_PC7 - PC7 */
-		gpio_port_power_switch		= <170>; /* GPIO_PV2 - PV2 */
-
-		/* GPIO polarity: 0=active_low, 1=active_high */
-		polarity_write_protect_switch	= <1>;
-		polarity_recovery_switch	= <0>;
-		polarity_developer_switch	= <1>;
-		polarity_lid_switch		= <0>;
-		polarity_power_switch		= <0>;
+		/* Chrome OS specific GPIO */
+		/*
+		 * Parameter 3 bits
+		 * bit 0: 1=output, 0=input
+		 * bit 1: 1=high, 0=low
+		 * bit 2: 1=active low, 0=active high
+		 */
+		write-protect-switch	= <&gpio 59 0>; /* GMI-AD11 - PH3 */
+		recovery-switch		= <&gpio 56 4>; /* GMI-AD08 - PH0 */
+		developer-switch	= <&gpio 168 0>; /* GPIO-PV0 - PV0 */
+		lid-switch		= <&gpio 23 4>; /* GPIO-PC7 - PC7 */
+		power-switch		= <&gpio 170 4>; /* GPIO-PV2 - PV2 */
 	};
 
 	aliases {
diff --git a/board/nvidia/seaboard/tegra2-asymptote.dts b/board/nvidia/seaboard/tegra2-asymptote.dts
index f1e6265ffce..1799a286c61 100644
--- a/board/nvidia/seaboard/tegra2-asymptote.dts
+++ b/board/nvidia/seaboard/tegra2-asymptote.dts
@@ -14,15 +14,16 @@
 		hwid = "ARM ASYMPTOTE TEST 8314";
 		machine-arch-id = <3624>;
 
-		/* Chrome OS specific GPIO port number */
-		gpio_port_write_protect_switch	= <59>;
-		gpio_port_recovery_switch	= <56>;
-		gpio_port_developer_switch	= <168>;
-
-		/* GPIO polarity: 0=active_low, 1=active_high */
-		polarity_write_protect_switch	= <1>;
-		polarity_recovery_switch	= <0>;
-		polarity_developer_switch	= <1>;
+		/* Chrome OS specific GPIO */
+		/*
+		 * Parameter 3 bits
+		 * bit 0: 1=output, 0=input
+		 * bit 1: 1=high, 0=low
+		 * bit 2: 1=active low, 0=active high
+		 */
+		write-protect-switch	= <&gpio 59 0>;
+		recovery-switch		= <&gpio 56 4>;
+		developer-switch	= <&gpio 168 0>;
 	};
 
 	aliases {
diff --git a/board/nvidia/seaboard/tegra2-kaen.dts b/board/nvidia/seaboard/tegra2-kaen.dts
index e11bd7adcd6..a79fd155410 100644
--- a/board/nvidia/seaboard/tegra2-kaen.dts
+++ b/board/nvidia/seaboard/tegra2-kaen.dts
@@ -14,19 +14,18 @@
 		hwid = "ARM KAEN TEST 3084";
 		machine-arch-id = <3217>;
 
-		/* Chrome OS specific GPIO port number */
-		gpio_port_write_protect_switch	= <59>;
-		gpio_port_recovery_switch	= <56>;
-		gpio_port_developer_switch	= <168>;
-		gpio_port_lid_switch		= <23>;
-		gpio_port_power_switch		= <170>;
-
-		/* GPIO polarity: 0=active_low, 1=active_high */
-		polarity_write_protect_switch	= <0>;
-		polarity_recovery_switch	= <0>;
-		polarity_developer_switch	= <1>;
-		polarity_lid_switch		= <0>;
-		polarity_power_switch		= <0>;
+		/* Chrome OS specific GPIO */
+		/*
+		 * Parameter 3 bits
+		 * bit 0: 1=output, 0=input
+		 * bit 1: 1=high, 0=low
+		 * bit 2: 1=active low, 0=active high
+		 */
+		write-protect-switch	= <&gpio 59 4>;
+		recovery-switch		= <&gpio 56 4>;
+		developer-switch	= <&gpio 168 0>;
+		lid-switch		= <&gpio 23 4>;
+		power-switch		= <&gpio 170 4>;
 	};
 
 	aliases {
diff --git a/board/nvidia/seaboard/tegra2-seaboard.dts b/board/nvidia/seaboard/tegra2-seaboard.dts
index ff5f1d395df..1e74e6fc97f 100644
--- a/board/nvidia/seaboard/tegra2-seaboard.dts
+++ b/board/nvidia/seaboard/tegra2-seaboard.dts
@@ -14,19 +14,18 @@
 		hwid = "ARM SEABOARD TEST 1176";
 		machine-arch-id = <3005>;
 
-		/* Chrome OS specific GPIO port number */
-		gpio_port_write_protect_switch	= <59>;
-		gpio_port_recovery_switch	= <56>;
-		gpio_port_developer_switch	= <168>;
-		gpio_port_lid_switch		= <23>;
-		gpio_port_power_switch		= <170>;
-
-		/* GPIO polarity: 0=active_low, 1=active_high */
-		polarity_write_protect_switch	= <1>;
-		polarity_recovery_switch	= <0>;
-		polarity_developer_switch	= <1>;
-		polarity_lid_switch		= <0>;
-		polarity_power_switch		= <0>;
+		/* Chrome OS specific GPIO */
+		/*
+		 * Parameter 3 bits
+		 * bit 0: 1=output, 0=input
+		 * bit 1: 1=high, 0=low
+		 * bit 2: 1=active low, 0=active high
+		 */
+		write-protect-switch	= <&gpio 59 0>;
+		recovery-switch		= <&gpio 56 4>;
+		developer-switch	= <&gpio 168 0>;
+		lid-switch		= <&gpio 23 4>;
+		power-switch		= <&gpio 170 4>;
 	};
 
 	aliases {