diff options
| author | Che-Liang Chiou <clchiou@chromium.org> | 2011-08-11 17:58:58 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2011-08-29 10:59:37 -0700 |
| commit | 046ef6142cfcb42150486f45fdd4fba95e0367fc (patch) | |
| tree | 1620ff58efae592aea38ccdceac0e6bafb7a50f4 /board/nvidia/seaboard/tegra2-arthur.dts | |
| parent | 8d920268a376a12087d846ee58190a4d2b0f5794 (diff) | |
CHROMIUM: decode GPIO configs through <&gpio ...>
cros_gpio module used a ad-hoc format of GPIO config, and it should
use <&gpio ...> instead. This patch changes the format of GPIO config.
Note: In between calls to gpio_direction_input() (in fdt_setup_gpio())
and calls to gpio_get_value(), you have to insert a small delay if the
input source is connected to the GPIO through a sufficiently large
series resister (say, 200K ohm) so that the RC time constant for
charging the gate capacitance on the input is non-trivial.
As a matter of fact, I tested on Kaen and Aebl, and found only write
protect GPIO needs this delay, and the delay time is less than 10 us.
And we may safely hide this delay by decoupling the initialization and
reading of GPIOs.
BUG=none
TEST=Run "vboot_test gpio" on Kaen and Aebl, and check GPIO readings
TEST=Run "crossystem" on Kaen and Aebl after boot, and check GPIO readings
Change-Id: Ib4d93c2ce156eb09ffc24a3882f83490d25c1e91
Reviewed-on: http://gerrit.chromium.org/gerrit/5726
Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Diffstat (limited to 'board/nvidia/seaboard/tegra2-arthur.dts')
| -rw-r--r-- | board/nvidia/seaboard/tegra2-arthur.dts | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/board/nvidia/seaboard/tegra2-arthur.dts b/board/nvidia/seaboard/tegra2-arthur.dts index 8e9edc14457..de598b39b78 100644 --- a/board/nvidia/seaboard/tegra2-arthur.dts +++ b/board/nvidia/seaboard/tegra2-arthur.dts @@ -14,19 +14,18 @@ hwid = "ARM ARTHUR TEST 3403"; machine-arch-id = <3474>; - /* Chrome OS specific GPIO port number */ - gpio_port_write_protect_switch = <59>; /* GMI_AD11 - PH3 */ - gpio_port_recovery_switch = <56>; /* GMI_AD08 - PH0 */ - gpio_port_developer_switch = <168>; /* GPIO_PV0 - PV0 */ - gpio_port_lid_switch = <23>; /* GPIO_PC7 - PC7 */ - gpio_port_power_switch = <170>; /* GPIO_PV2 - PV2 */ - - /* GPIO polarity: 0=active_low, 1=active_high */ - polarity_write_protect_switch = <1>; - polarity_recovery_switch = <0>; - polarity_developer_switch = <1>; - polarity_lid_switch = <0>; - polarity_power_switch = <0>; + /* Chrome OS specific GPIO */ + /* + * Parameter 3 bits + * bit 0: 1=output, 0=input + * bit 1: 1=high, 0=low + * bit 2: 1=active low, 0=active high + */ + write-protect-switch = <&gpio 59 0>; /* GMI-AD11 - PH3 */ + recovery-switch = <&gpio 56 4>; /* GMI-AD08 - PH0 */ + developer-switch = <&gpio 168 0>; /* GPIO-PV0 - PV0 */ + lid-switch = <&gpio 23 4>; /* GPIO-PC7 - PC7 */ + power-switch = <&gpio 170 4>; /* GPIO-PV2 - PV2 */ }; aliases { |