diff options
| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-01-17 17:07:14 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-01-23 18:26:44 +0100 |
| commit | 2f8d0677366d859bd2f23fc58280e913f15a4f61 (patch) | |
| tree | c91e03e26444d6893dd46b5a08d596cb70ab03b7 /board/mscc | |
| parent | c8546163fa92bb46c09017db18dadbb26e639895 (diff) | |
MIPS: mscc: ocelot: add switch reset support
On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'board/mscc')
| -rw-r--r-- | board/mscc/ocelot/ocelot.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index 0f7a532158..532d06f000 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -10,6 +10,7 @@ #include <environment.h> #include <spi.h> #include <led.h> +#include <wait_bit.h> DECLARE_GLOBAL_DATA_PTR; @@ -18,6 +19,29 @@ enum { BOARD_TYPE_PCB123, }; +void mscc_switch_reset(bool enter) +{ + /* Nasty workaround to avoid GPIO19 (DDR!) being reset */ + mscc_gpio_set_alternate(19, 2); + + debug("applying SwC reset\n"); + + writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); + writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); + + if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST, + PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false)) + pr_err("Tiemout while waiting for switch reset\n"); + + /* + * Reset GPIO19 mode back as regular GPIO, output, high (DDR + * not reset) (Order is important) + */ + setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); + writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); + mscc_gpio_set_alternate(19, 0); +} + void board_debug_uart_init(void) { /* too early for the pinctrl driver, so configure the UART pins here */ |