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authorStefan Roese <sr@denx.de>2009-09-24 09:55:50 +0200
committerStefan Roese <sr@denx.de>2009-09-28 10:45:42 +0200
commit952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 (patch)
treeabd867c1a44dbc20bbd970c36c76f0355adc6df4 /board/mpl
parent984f10baac8ef6032df52f135943d6b0bc96f724 (diff)
ppc4xx: Convert PPC4xx UIC defines from lower case to upper case
The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/mpl')
-rw-r--r--board/mpl/mip405/mip405.c14
-rw-r--r--board/mpl/pip405/pip405.c14
2 files changed, 14 insertions, 14 deletions
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index d8279e81c98..b87df01fec2 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -489,13 +489,13 @@ int board_early_init_f (void)
| caused the interrupt.
|
+-------------------------------------------------------------------------*/
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (uicer, 0x00000000); /* disable all ints */
- mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
- mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
- mtdcr (uictr, 0x10000000); /* set int trigger levels */
- mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
+ mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index e00d1d08f5c..c2d6c6fbcfa 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -552,13 +552,13 @@ int board_early_init_f (void)
| caused the interrupt.
|
+-------------------------------------------------------------------------*/
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (uicer, 0x00000000); /* disable all ints */
- mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
- mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
- mtdcr (uictr, 0x10000000); /* set int trigger levels */
- mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
+ mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
+ mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}