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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-10-16 15:01:15 +0200
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:03 +0200
commit6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch)
treeae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/mpl/pip405
parent71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff)
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/mpl/pip405')
-rw-r--r--board/mpl/pip405/pip405.c6
-rw-r--r--board/mpl/pip405/pip405.h2
2 files changed, 4 insertions, 4 deletions
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index 6cba892e78..3be0104709 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -208,7 +208,7 @@ int board_early_init_f (void)
#endif
/* Read Serial Presence Detect Information */
- i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
dataout[0] = 0;
for (i = 0; i < 128; i++)
datain[i] = 127;
@@ -386,7 +386,7 @@ int board_early_init_f (void)
/* write SDRAM timing register */
mtdcr (memcfga, mem_sdtr1);
mtdcr (memcfgd, tmp);
- baseaddr = CFG_SDRAM_BASE;
+ baseaddr = CONFIG_SYS_SDRAM_BASE;
bank_size = (((unsigned long) density) << 22) / 2;
/* insert AM value */
tmp = ((unsigned long) t->mode - 1) << 13;
@@ -663,7 +663,7 @@ int misc_init_r (void)
{
/* adjust flash start and size as well as the offset */
gd->bd->bi_flashstart=0-flash_info[0].size;
- gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+ gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
gd->bd->bi_flashoffset=0;
/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
index 5815786ebf..704ab2c71d 100644
--- a/board/mpl/pip405/pip405.h
+++ b/board/mpl/pip405/pip405.h
@@ -35,7 +35,7 @@ void user_led0(unsigned char on);
void user_led1(unsigned char on);
-#define PLD_BASE_ADDRESS CFG_ISA_IO_BASE_ADDRESS + 0x800
+#define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800
#define PLD_PART_REG PLD_BASE_ADDRESS + 0
#define PLD_VERS_REG PLD_BASE_ADDRESS + 1
#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2