diff options
author | Michal Simek <monstr@monstr.eu> | 2007-05-08 00:32:35 +0200 |
---|---|---|
committer | Michal Simek <monstr@monstr.eu> | 2007-05-08 00:32:35 +0200 |
commit | 3c4bd60de15d79ddfc0cf3170a55847b2025d93f (patch) | |
tree | 891b84b58f13a5f45536a243585b9d94c253a410 /board/mpc8349emds/mpc8349emds.c | |
parent | fb05f6da35ea1c15c553abe6f23f656bf18dc5db (diff) | |
parent | ac4cd59d59c9bf3f89cb7a344abf8184d678f562 (diff) |
Merge git://www.denx.de/git/u-boot
Conflicts:
include/asm-microblaze/microblaze_intc.h
include/linux/stat.h
Diffstat (limited to 'board/mpc8349emds/mpc8349emds.c')
-rw-r--r-- | board/mpc8349emds/mpc8349emds.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 873bdd01cd6..071591ed835 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -119,6 +119,20 @@ int fixed_sdram(void) #if (CFG_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif +#ifdef CONFIG_DDR_II + im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; + im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; +#else im->ddr.csbnds[2].csbnds = 0x0000000f; im->ddr.cs_config[2] = CFG_DDR_CONFIG; @@ -143,6 +157,7 @@ int fixed_sdram(void) im->ddr.sdram_mode = CFG_DDR_MODE; im->ddr.sdram_interval = CFG_DDR_INTERVAL; +#endif udelay(200); /* enable DDR controller */ @@ -239,7 +254,7 @@ void sdram_init(void) #else void sdram_init(void) { - put("SDRAM on Local Bus is NOT available!\n"); + puts(" SDRAM on Local Bus is NOT available!\n"); } #endif |