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authorwdenk <wdenk>2002-11-03 00:38:21 +0000
committerwdenk <wdenk>2002-11-03 00:38:21 +0000
commitfe8c2806cdba70479e351299881a395dc2be7785 (patch)
treea1e8b98a1838cba6e6f5c765d9d85339257c45f5 /board/mousse
parentf9087a3213cc245cf9b90436475b5af822bd7579 (diff)
Initial revision
Diffstat (limited to 'board/mousse')
-rw-r--r--board/mousse/README350
-rw-r--r--board/mousse/mousse.h259
2 files changed, 609 insertions, 0 deletions
diff --git a/board/mousse/README b/board/mousse/README
new file mode 100644
index 00000000000..ef072bd92ff
--- /dev/null
+++ b/board/mousse/README
@@ -0,0 +1,350 @@
+
+U-Boot for MOUSSE/MPC8240 (KAHLUA)
+----------------------------------
+James Dougherty (jfd@broadcom.com), 09/10/01
+
+The Broadcom/Vooha Mousse board is a 3U Compact PCI system board
+which uses the MPC8240, a 64MB SDRAM SIMM, and has onboard
+DEC 21143, NS16550 UART, an SGS M48T59Y TOD, and 4MB FLASH.
+See also: http://www.vooha.com/
+
+* NVRAM setenv/printenv/savenv supported.
+* Date Command
+* Serial Console support
+* Network support
+* FLASH of kernel images is supported.
+* FLASH of U-Boot to onboard and PLCC boot region.
+* Kernel command line options from NVRAM is supported.
+* IP PNP options supported.
+
+U-Boot Loading...
+
+
+
+U-Boot 1.0.5 (Sep 10 2001 - 00:22:25)
+
+CPU: MPC8240 Revision 1.1 at 198 MHz: 16 kB I-Cache 16 kB D-Cache
+Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)
+Built: Sep 10 2001 at 01:01:50
+MPLD: Revision 127
+Local Bus: 33 MHz
+RTC: M48T589 TOD/NVRAM (8176) bytes
+ Current date/time: 9/10/2001 0:18:52
+DRAM: 64 MB
+FLASH: 1.960 MB
+PCI: scanning bus0 ...
+ bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE
+ 00 00 00 1057 0003 060000 11 00000008 00000000 01 00
+ 00 0d 00 1011 0019 020000 41 80000001 80000000 01 01
+ 00 0e 00 105a 4d38 018000 01 a0000001 a0001001 01 03
+In: serial
+Out: serial
+Err: serial
+
+Hit any key to stop autoboot: 0
+=>
+
+I. Root FileSystem/IP Configuration
+
+bootcmd=tftp 100000 vmlinux.img;bootm
+bootdelay=3
+baudrate=9600
+ipaddr=<IP ADDRESS>
+netmask=<NETMASK>
+hostname=<NAME>
+serverip=<NFS SERVER IP ADDRESS>
+ethaddr=00:00:10:20:30:44
+nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs
+gateway=<IP ADDRESS>
+root=/dev/nfs
+stdin=serial
+stdout=serial
+stderr=serial
+
+NVRAM environment variables.
+
+use the command:
+
+setenv <attribute> <value>
+
+type "saveenv" to write to NVRAM.
+
+
+
+II. To boot from a hard drive:
+
+setenv root /dev/hda1
+
+
+III. IP options which configure the network:
+
+ipaddr=<IP ADDRESS OF MACHINE>
+netmask=<NETMASK>
+hostname=mousse
+ethaddr=00:00:10:20:30:44
+gateway=<IP ADDRESS OF GATEWAY/ROUTER>
+
+
+IV. IP Options which configure NFS Root/Boot Support
+
+root=/dev/nfs
+serverip=<NFS SERVER IP ADDRESS>
+nfsroot=<NFS SERVER IP ADDRESS>:/boot/root-fs
+
+V. U-Boot Image Support
+
+The U-Boot boot loader assumes that after you build
+your kernel (vmlinux), you will create a U-Boot image
+using the following commands or script:
+
+#!/bin/csh
+/bin/touch vmlinux.img
+/bin/rm vmlinux.img
+set path=($TOOLBASE/bin $path)
+set path=($U_BOOT/tools $path)
+powerpc-linux-objcopy -S -O binary vmlinux vmlinux.bin
+gzip -vf vmlinux.bin
+mkimage -A ppc -O linux -T kernel -C gzip -a 0 -e 0 -n vmlinux.bin.gz -d vmlinux.bin.gz vmlinux.img
+ls -l vmlinux.img
+
+
+VI. ONBOARD FLASH Support
+
+FLASH support is provided for the onboard FLASH chip Bootrom area.
+U-Boot is loaded into either the ROM boot region of the FLASH chip,
+after first being boot-strapped from a pre-progammed AMD29F040 PLCC
+bootrom. The PLCC needs to be programmed with a ROM burner using
+AMD 29F040 ROM parts and the u-boot.bin or u-boot.hex (S-Record)
+images.
+
+The PLCC overlays this same region of flash as the onboard FLASH,
+the jumper J100 is a chip-select for which flash chip you want to
+progam. When jumper J100 is connected to pins 2-3, you boot from
+PLCC FLASH.
+
+To bringup a system, simply flash a flash an AMD29F040 PLCC
+bootrom, and put this in the PLCC socket. Move jumper J100 to
+pins 2-3 and boot from the PLCC.
+
+
+Now, while the system is running, move Jumper J100 to
+pins 1-2 and follow the procedure below to FLASH a bootrom
+(u-boot.bin) image into the onboard bootrom region (AMD29LV160DB):
+
+tftp 100000 u-boot.bin
+protect off FFF00000 FFF7FFFF
+erase FFF00000 FFF7FFFF
+cp.b 100000 FFF00000 \$(filesize)\
+
+
+Here is an example:
+
+=>tftp 100000 u-boot.bin
+eth_halt
+eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0)
+DEC Ethernet iobase=0x80000000
+ARP broadcast 1
+Filename 'u-boot.bin'.
+Load address: 0x100000
+Loading: #########################
+done
+Bytes transferred = 123220 (1e154 hex)
+eth_halt
+=>protect off FFF00000 FFF7FFFF
+Un-Protected 8 sectors
+=>erase FFF00000 FFF7FFFF
+Erase Flash from 0xfff00000 to 0xfff7ffff
+Erase FLASH[PLCC_BOOT] -8 sectors:........ done
+Erased 8 sectors
+=>cp.b 100000 FFF00000 1e154
+Copy to Flash... FLASH[PLCC_BOOT]:..done
+=>
+
+
+B. FLASH RAMDISK REGION
+
+FLASH support is provided for an Onboard 512K RAMDISK region.
+
+TThe following commands will FLASH a bootrom (u-boot.bin) image
+into the onboard FLASH region (AMD29LV160DB 2MB FLASH):
+
+tftp 100000 u-boot.bin
+protect off FFF80000 FFFFFFFF
+erase FFF80000 FFFFFFFF
+cp.b 100000 FFF80000 \$(filesize)\
+
+
+
+C. FLASH KERNEL REGION (960KB)
+
+FLASH support is provided for the 960KB onboard FLASH1 segment.
+This allows flashing of kernel images which U-Boot can load
+and run (standalone) from the onboard FLASH chip. It also assumes
+
+The following commands will FLASH a kernel image to 0xffe10000
+
+tftp 100000 vmlinux.img
+protect off FFE10000 FFEFFFFF
+erase FFE10000 FFEFFFFF
+cp.b 100000 FFE10000 \$(filesize)\
+reset
+
+Here is an example:
+
+
+=>tftp 100000 vmlinux.img
+eth_halt
+eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0)
+DEC Ethernet iobase=0x80000000
+ARP broadcast 1
+TFTP from server 209.128.93.133; our IP address is 209.128.93.138
+Filename 'vmlinux.img'.
+Load address: 0x100000
+Loading: #####################################################################################################################################################
+done
+Bytes transferred = 760231 (b99a7 hex)
+eth_halt
+=>protect off FFE10000 FFEFFFFF
+Un-Protected 15 sectors
+=>erase FFE10000 FFEFFFFF
+Erase Flash from 0xffe10000 to 0xffefffff
+Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done
+Erased 15 sectors
+=>cp.b 100000 FFE10000 b99a7
+Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done
+=>
+
+
+
+When finished, use the command:
+
+bootm ffe10000
+
+to start the kernel.
+
+Finally, to make this the default boot command, use
+the following commands:
+
+setenv bootcmd bootm ffe10000
+savenv
+
+to make it automatically boot the kernel from FLASH.
+
+
+To go back to development mode (NFS boot)
+
+setenv bootcmd tftp 100000 vmlinux.img\;bootm
+savenv
+
+
+=>tftp 100000 vmlinux.img
+eth0: DC21143 Ethernet adapter(bus=0, device=13, func=0)
+DEC Ethernet iobase=0x80000000
+ARP broadcast 1
+Filename 'vmlinux.img'.
+Load address: 0x100000
+Loading: ####################################################################################################################################################
+done
+Bytes transferred = 752717 (b7c4d hex)
+eth_halt
+=>protect off FFE10000 FFEFFFFF
+Un-Protected 15 sectors
+=>erase FFE10000 FFEFFFFF
+Erase Flash from 0xffe10000 to 0xffefffff
+Erase FLASH[F0_SA3(KERNEL)] -15 sectors:............... done
+Erased 15 sectors
+=>cp.b 100000 FFE10000 b7c4d
+Copy to Flash... FLASH[F0_SA3(KERNEL)]:............done
+=>bootm ffe10000
+## Booting image at ffe10000 ...
+ Image Name: vmlinux.bin.gz
+ Image Type: PowerPC Linux Kernel Image (gzip compressed)
+ Data Size: 752653 Bytes = 735 kB = 0 MB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+ Uncompressing Kernel Image ... OK
+Total memory = 64MB; using 0kB for hash table (at 00000000)
+Linux version 2.4.2_hhl20 (jfd@atlantis) (gcc version 2.95.2 19991024 (release)) #597 Wed Sep 5 23:23:23 PDT 2001
+cpu0: MPC8240/KAHLUA : MOUSSE Platform : 64MB RAM: MPLD Rev. 7f
+Sandpoint port (C) 2000, 2001 MontaVista Software, Inc. (source@mvista.com)
+IP PNP: 802.3 Ethernet Address=<0:0:10:20:30:44>
+NOTICE: mounting root file system via NFS
+On node 0 totalpages: 16384
+zone(0): 16384 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+time_init: decrementer frequency = 16.665914 MHz
+time_init: MPC8240 PCI Bus frequency = 33.331828 MHz
+Calibrating delay loop... 133.12 BogoMIPS
+Memory: 62436k available (1336k kernel code, 500k data, 88k init, 0k highmem)
+Dentry-cache hash table entries: 8192 (order: 4, 65536 bytes)
+Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes)
+Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
+Inode-cache hash table entries: 4096 (order: 3, 32768 bytes)
+POSIX conformance testing by UNIFIX
+PCI: Probing PCI hardware
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Initializing RT netlink socket
+Starting kswapd v1.8
+pty: 256 Unix98 ptys configured
+block: queued sectors max/low 41394kB/13798kB, 128 slots per queue
+Uniform Multi-Platform E-IDE driver Revision: 6.31
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
+PDC20262: IDE controller on PCI bus 00 dev 70
+PDC20262: chipset revision 1
+PDC20262: not 100% native mode: will probe irqs later
+PDC20262: ROM enabled at 0x000d0000
+PDC20262: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.
+PDC20262: FORCING BURST BIT 0x00 -> 0x01 ACTIVE
+PDC20262: irq=3 dev->irq=3
+ ide0: BM-DMA at 0xbfff00-0xbfff07, BIOS settings: hda:DMA, hdb:DMA
+ ide1: BM-DMA at 0xbfff08-0xbfff0f, BIOS settings: hdc:pio, hdd:pio
+hda: WDC WD300AB-00BVA0, ATA DISK drive
+hdc: SONY CD-RW CRX160E, ATAPI CD/DVD-ROM drive
+ide0 at 0xbfff78-0xbfff7f,0xbfff76 on irq 3
+ide1 at 0xbfff68-0xbfff6f,0xbfff66 on irq 3
+hda: 58633344 sectors (30020 MB) w/2048KiB Cache, CHS=58168/16/63, UDMA(66)
+hdc: ATAPI 32X CD-ROM CD-R/RW drive, 4096kB Cache
+Uniform CD-ROM driver Revision: 3.12
+Partition check:
+ /dev/ide/host0/bus0/target0/lun0: p1 p2
+hd: unable to get major 3 for hard disk
+udf: registering filesystem
+loop: loaded (max 8 devices)
+Serial driver version 5.02 (2000-08-09) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
+ttyS00 at 0xffe08080 (irq = 4) is a ST16650
+Linux Tulip driver version 0.9.13a (January 20, 2001)
+eth0: Digital DS21143 Tulip rev 65 at 0xbfff80, EEPROM not present, 00:00:10:20:30:44, IRQ 1.
+eth0: MII transceiver #0 config 3000 status 7829 advertising 01e1.
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP
+IP: routing cache hash table of 512 buckets, 4Kbytes
+TCP: Hash tables configured (established 4096 bind 4096)
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+devfs: v0.102 (20000622) Richard Gooch (rgooch@atnf.csiro.au)
+devfs: boot_options: 0x0
+VFS: Mounted root (nfs filesystem).
+Mounted devfs on /dev
+Freeing unused kernel memory: 88k init 4k openfirmware
+eth0: Setting full-duplex based on MII#0 link partner capability of 45e1.
+INIT: version 2.78 booting
+INIT: Entering runlevel: 2
+
+
+Welcome to Linux/PPC
+MPC8240/MOUSSE
+
+
+mousse login: root
+Password:
+PAM_unix[13]: (login) session opened for user root by LOGIN(uid=0)
+Last login: Thu Sep 6 00:16:51 2001 on console
+
+
+Welcome to Linux/PPC
+MPC8240/MOUSSE
+
+
+mousse#
diff --git a/board/mousse/mousse.h b/board/mousse/mousse.h
new file mode 100644
index 00000000000..5468314eb72
--- /dev/null
+++ b/board/mousse/mousse.h
@@ -0,0 +1,259 @@
+/*
+ * MOUSSE/MPC8240 Board definitions.
+ * For more info, see http://www.vooha.com/
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James Dougherty (jfd@cs.stanford.edu)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MOUSSE_H
+#define __MOUSSE_H
+
+/* System addresses */
+
+#define PCI_SPECIAL_BASE 0xfe000000
+#define PCI_SPECIAL_SIZE 0x01000000
+
+/* PORTX Device Addresses for Mousse */
+
+#define PORTX_DEV_BASE 0xff000000
+#define PORTX_DEV_SIZE 0x01000000
+
+#define ENET_DEV_BASE 0x80000000
+
+#define PLD_REG_BASE (PORTX_DEV_BASE | 0xe09000)
+#define PLD_REG(off) (*(volatile unsigned char *) \
+ (PLD_REG_BASE + (off)))
+
+#define PLD_REVID_B1 0x7f
+#define PLD_REVID_B2 0x01
+
+/* MPLD */
+#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
+#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f)
+#define SYS_LED_OFF() (PLD_REG(1) |= 0x80)
+#define SYS_LED_ON() (PLD_REG(1) &= ~0x80)
+#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80)
+#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80)
+#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80)
+#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80)
+
+/* SGS M48T59Y */
+#define TOD_BASE (PORTX_DEV_BASE | 0xe0a000)
+#define TOD_REG_BASE (TOD_BASE | 0x1ff0)
+#define TOD_NVRAM_BASE TOD_BASE
+#define TOD_NVRAM_SIZE 0x1ff0
+#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
+
+/* NS16552 SIO */
+#define SERIAL_BASE(_x) (PORTX_DEV_BASE | 0xe08000 | ((_x) ? 0 : 0x80))
+#define N_SIO_CHANNELS 2
+#define N_COM_PORTS N_SIO_CHANNELS
+
+/*
+ * On-board Dec21143 PCI Ethernet
+ * Note: The PCI MBAR chosen here was used from MPC8240UM which states
+ * that PCI memory is at: 0x80000 - 0xFDFFFFFF, if AMBOR[CPU_FD_ALIAS]
+ * is set, then PCI memory maps 1-1 with this address range in the
+ * correct byte order.
+ */
+#define PCI_ENET_IOADDR 0x80000000
+#define PCI_ENET_MEMADDR 0x80000000
+
+/*
+ * Flash Memory Layout
+ *
+ * 2 MB Flash Bank 0 runs in 8-bit mode. In Flash Bank 0, the 32 kB
+ * sector SA3 is obscured by the 32 kB serial/TOD access space, and
+ * the 64 kB sectors SA19-SA26 are obscured by the 512 kB PLCC
+ * containing the fixed boot ROM. (If the 512 kB PLCC is
+ * deconfigured by jumper, this window to Flash Bank 0 becomes
+ * visible, but it still contains the fixed boot code and should be
+ * considered read-only). Flash Bank 0 sectors SA0 (16 kB), SA1 (8
+ * kB), and SA2 (8 kB) are currently unused.
+ *
+ * 2 MB Flash Bank 1 runs in 16-bit mode. Flash Bank 1 is fully
+ * usable, but it's a 16-bit wide device on a 64-bit bus. Therefore
+ * 16-bit words only exist at addresses that are multiples of 8. All
+ * PROM data and control addresses must be multiplied by 8.
+ *
+ * See flashMap.c for description of flash filesystem layout.
+ */
+
+/*
+ * FLASH memory address space: 8-bit wide FLASH memory spaces.
+ */
+#define FLASH0_SEG0_START 0xffe00000 /* Baby 32Kb segment */
+#define FLASH0_SEG0_END 0xffe07fff /* 16 kB + 8 kB + 8 kB */
+#define FLASH0_SEG0_SIZE 0x00008000 /* (sectors SA0-SA2) */
+
+#define FLASH0_SEG1_START 0xffe10000 /* 1MB - 64Kb FLASH0 seg */
+#define FLASH0_SEG1_END 0xffefffff /* 960 kB */
+#define FLASH0_SEG1_SIZE 0x000f0000
+
+#define FLASH0_SEG2_START 0xfff00000 /* Boot Loader stored here */
+#define FLASH0_SEG2_END 0xfff7ffff /* 512 kB FLASH0/PLCC seg */
+#define FLASH0_SEG2_SIZE 0x00080000
+
+#define FLASH0_SEG3_START 0xfff80000 /* 512 kB FLASH0 seg */
+#define FLASH0_SEG3_END 0xffffffff
+#define FLASH0_SEG3_SIZE 0x00080000
+
+/* Where Kahlua starts */
+#define FLASH_RESET_VECT 0xfff00100
+
+/*
+ * CHRP / PREP (MAP A/B) definitions.
+ */
+
+#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */
+#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */
+/* MPC107 (MPC8240 internal EUMBBAR mapped) */
+#define CHRP_REG_ADDR 0xfec00000 /* MPC106 Config, Map B */
+#define CHRP_REG_DATA 0xfee00000 /* MPC106 Config, Map B */
+
+/*
+ * Mousse PCI IDSEL Assignments (Device Number)
+ */
+#define MOUSSE_IDSEL_ENET 13 /* On-board 21143 Ethernet */
+#define MOUSSE_IDSEL_LPCI 14 /* On-board PCI slot */
+#define MOUSSE_IDSEL_82371 15 /* That other thing */
+#define MOUSSE_IDSEL_CPCI2 31 /* CPCI slot 2 */
+#define MOUSSE_IDSEL_CPCI3 30 /* CPCI slot 3 */
+#define MOUSSE_IDSEL_CPCI4 29 /* CPCI slot 4 */
+#define MOUSSE_IDSEL_CPCI5 28 /* CPCI slot 5 */
+#define MOUSSE_IDSEL_CPCI6 27 /* CPCI slot 6 */
+
+/*
+ * Mousse Interrupt Mapping:
+ *
+ * IRQ1 Enet (intA|intB|intC|intD)
+ * IRQ2 CPCI intA (See below)
+ * IRQ3 Local PCI slot intA|intB|intC|intD
+ * IRQ4 COM1 Serial port (Actually higher addressed port on duart)
+ *
+ * PCI Interrupt Mapping in CPCI chassis:
+ *
+ * | CPCI Slot
+ * | 1 (CPU) 2 3 4 5 6
+ * -----------+--------+-------+-------+-------+-------+-------+
+ * intA | X X X
+ * intB | X X X
+ * intC | X X X
+ * intD | X X X
+ */
+
+
+#define EPIC_VECTOR_EXT0 0
+#define EPIC_VECTOR_EXT1 1
+#define EPIC_VECTOR_EXT2 2
+#define EPIC_VECTOR_EXT3 3
+#define EPIC_VECTOR_EXT4 4
+#define EPIC_VECTOR_TM0 16
+#define EPIC_VECTOR_TM1 17
+#define EPIC_VECTOR_TM2 18
+#define EPIC_VECTOR_TM3 19
+#define EPIC_VECTOR_I2C 20
+#define EPIC_VECTOR_DMA0 21
+#define EPIC_VECTOR_DMA1 22
+#define EPIC_VECTOR_I2O 23
+
+
+#define INT_VEC_IRQ0 0
+#define INT_NUM_IRQ0 INT_VEC_IRQ0
+#define MOUSSE_IRQ_ENET EPIC_VECTOR_EXT1 /* Hardwired */
+#define MOUSSE_IRQ_CPCI EPIC_VECTOR_EXT2 /* Hardwired */
+#define MOUSSE_IRQ_LPCI EPIC_VECTOR_EXT3 /* Hardwired */
+#define MOUSSE_IRQ_DUART EPIC_VECTOR_EXT4 /* Hardwired */
+
+/* Onboard DEC 21143 Ethernet */
+#define PCI_ENET_MEMADDR 0x80000000
+#define PCI_ENET_IOADDR 0x80000000
+
+/* Some other PCI device */
+#define PCI_SLOT_MEMADDR 0x81000000
+#define PCI_SLOT_IOADDR 0x81000000
+
+/* Promise ATA66 PCI Device (ATA controller) */
+#define PROMISE_MBAR0 0xa0000000
+#define PROMISE_MBAR1 (PROMISE_MBAR0 + 0x1000)
+#define PROMISE_MBAR2 (PROMISE_MBAR0 + 0x2000)
+#define PROMISE_MBAR3 (PROMISE_MBAR0 + 0x3000)
+#define PROMISE_MBAR4 (PROMISE_MBAR0 + 0x4000)
+#define PROMISE_MBAR5 (PROMISE_MBAR0 + 0x5000)
+
+/* ATA/66 Controller offsets */
+#define CFG_ATA_BASE_ADDR PROMISE_MBAR0
+#define CFG_IDE_MAXBUS 2 /* ide0/ide1 */
+#define CFG_IDE_MAXDEVICE 2 /* 2 drives per controller */
+#define CFG_ATA_IDE0_OFFSET 0
+#define CFG_ATA_IDE1_OFFSET 0x3000
+/*
+ * Definitions for accessing IDE controller registers
+ */
+#define CFG_ATA_DATA_OFFSET 0
+#define CFG_ATA_REG_OFFSET 0
+#define CFG_ATA_ALT_OFFSET (0x1000)
+
+/*
+ * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
+ * are defined in config.h and Makefile.
+ * All definitions for these constants must be identical.
+ */
+#define ROM_BASE_ADRS 0xfff00000 /* base address of ROM */
+#define ROM_TEXT_ADRS (ROM_BASE_ADRS+0x0100) /* with PC & SP */
+#define ROM_WARM_ADRS (ROM_TEXT_ADRS+0x0004) /* warm reboot entry */
+#define ROM_SIZE 0x00080000 /* 512KB ROM space */
+#define RAM_LOW_ADRS 0x00010000 /* RAM address for vxWorks */
+#define RAM_HIGH_ADRS 0x00c00000 /* RAM address for bootrom */
+
+/*
+ * NVRAM configuration
+ * NVRAM is implemented via the SGS Thomson M48T59Y
+ * 64Kbit (8Kbx8) Timekeeper SRAM.
+ * This 8KB NVRAM also has a TOD. See m48t59y.{h,c} for more information.
+ */
+
+#define NV_RAM_ADRS TOD_NVRAM_BASE
+#define NV_RAM_INTRVL 1
+#define NV_RAM_WR_ENBL SYS_TOD_UNPROTECT()
+#define NV_RAM_WR_DSBL SYS_TOD_PROTECT()
+
+#define NV_OFF_BOOT0 0x0000 /* Boot string 0 (256b) */
+#define NV_OFF_BOOT1 0x0100 /* Boot string 1 (256b) */
+#define NV_OFF_BOOT2 0x0200 /* Boot string 2 (256b)*/
+#define NV_OFF_MACADDR 0x0400 /* 21143 MAC address (6b) */
+#define NV_OFF_ACTIVEBOOT 0x0406 /* Active boot string, 0 to 2 (1b) */
+#define NV_OFF_UNUSED1 0x0407 /* Unused (1b) */
+#define NV_OFF_BINDFIX 0x0408 /* See sysLib.c:sysBindFix() (1b) */
+#define NV_OFF_UNUSED2 0x0409 /* Unused (7b) */
+#define NV_OFF_TIMEZONE 0x0410 /* TIMEZONE env var (64b) */
+#define NV_OFF_VXWORKS_END 0x07FF /* 2047 VxWorks Total */
+#define NV_OFF_U_BOOT 0x0800 /* 2048 U-Boot boot-loader */
+#define NV_OFF_U_BOOT_ADDR (TOD_BASE + NV_OFF_U_BOOT) /* sysaddr*/
+#define NV_U_BOOT_ENV_SIZE 2048 /* 2K - U-Boot Total */
+#define NV_OFF__next_free (NV_U_BOOT_ENVSIZE +1)
+#define NV_RAM_SIZE 8176 /* NVRAM End */
+
+#endif /* __MOUSSE_H */