avr32: refactor the portmux/gpio code

  - Separate the portmux configuration functionality from the GPIO pin
    control API.
  - Separate the controller-specific code from the chip-specific code.
  - Allow "ganged" port configuration (multiple pins at once).
  - Add more flexibility to the "canned" peripheral select functions:
      - Allow using more than 23 address bits, more chip selects, as
	well as NAND- and CF-specific pins.
      - Make the MACB SPEED pin optional, and choose between MII/RMII
	using a parameter instead of an #ifdef.
      - Make it possible to use other MMC slots than slot 0, and support
	different MMC/SDCard data bus widths.
  - Use more reasonable pull-up defaults; floating pins may consume a
    lot of power.
  - Get rid of some custom portmux code from the mimc200 board code. The
    old gpio/portmux API couldn't really handle its requirements, but
    the new one can.
  - Add documentation.

The end result is slightly smaller code for all boards. Which isn't
really the point, but at least it isn't any larger.

This has been verified on ATSTK1002 and ATNGW100. I'd appreciate if
the board maintainers could help me test this on their boards. In
particular, the mimc200 port has lost a lot of code, so I'm hoping Mark
can help me out.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Cc: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Cc: Mark Jackson <mpfj@mimc.co.uk>
Cc: Alex Raimondi <alex.raimondi@miromico.ch>
Cc: Julien May <julien.may@miromico.ch>

Changes since v1:
  * Enable pullup on NWAIT
  * Add missing include to portmux-pio.h
  * Rename CONFIG_PIO2 -> CONFIG_PORTMUX_PIO to match docs

1 files changed, 6 insertions, 6 deletions

diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c
index 738ece2fe32..3d6cf9b28b8 100644
--- a/board/miromico/hammerhead/hammerhead.c
+++ b/board/miromico/hammerhead/hammerhead.c
@@ -29,9 +29,9 @@
 #include <asm/io.h>
 #include <asm/sdram.h>
 #include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
 #include <asm/arch/hmatrix.h>
 #include <asm/arch/memory-map.h>
+#include <asm/arch/portmux.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,14 +65,14 @@ int board_early_init_f(void)
 	/* Enable SDRAM in the EBI mux */
 	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
 
-	gpio_enable_ebi();
-	gpio_enable_usart1();
+	portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
 
 #if defined(CONFIG_MACB)
-	gpio_enable_macb0();
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
 #endif
 #if defined(CONFIG_MMC)
-	gpio_enable_mmci();
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
 #endif
 	return 0;
 }
@@ -107,7 +107,7 @@ void gclk_init(void)
 	/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
 
 	/* Select GCLK3 peripheral function */
-	gpio_select_periph_A(GPIO_PIN_PB29, 0);
+	portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29, PORTMUX_FUNC_A, 0);
 
 	/* Enable GCLK3 with no input divider, from OSC0 (crystal) */
 	sm_writel(PM_GCCTRL(3), SM_BIT(CEN));