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authorPaul Burton <paul.burton@imgtec.com>2016-05-27 14:28:05 +0100
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2016-05-31 09:44:24 +0200
commit372286217f050bfd57695001d59f618c52822f40 (patch)
treee2d926d936e6d65f2a229b19a347435f9f1d8d56 /board/micronas
parentace3be4f15875d74344336b9754c14274f940969 (diff)
MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'board/micronas')
-rw-r--r--board/micronas/vct/Kconfig5
1 files changed, 4 insertions, 1 deletions
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index 5bb6f03f30..df7c0296c7 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
config SYS_DCACHE_SIZE
default 16384
+config SYS_DCACHE_LINE_SIZE
+ default 32
+
config SYS_ICACHE_SIZE
default 16384
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
default 32
menu "vct board options"