arm: mx6: novena: Pull video handling into separate file

Pull all of the video handling into a separate file, since a lot
more code will be added and such code would polute the board file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>

4 files changed, 106 insertions, 78 deletions

diff --git a/board/kosagi/novena/Makefile b/board/kosagi/novena/Makefile
index 6fba17718b7..6893b6311d6 100644
--- a/board/kosagi/novena/Makefile
+++ b/board/kosagi/novena/Makefile
@@ -8,4 +8,5 @@ ifdef CONFIG_SPL_BUILD
 obj-y	:= novena_spl.o
 else
 obj-y	:= novena.o
+obj-$(CONFIG_VIDEO_IPUV3)	+= video.o
 endif
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
index 5493e07c02e..e7a6adb6115 100644
--- a/board/kosagi/novena/novena.c
+++ b/board/kosagi/novena/novena.c
@@ -152,87 +152,10 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-/*
- * Video over HDMI
- */
-#if defined(CONFIG_VIDEO_IPUV3)
-static void enable_hdmi(struct display_info_t const *dev)
-{
-	imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {
-	{
-		/* HDMI Output */
-		.bus	= -1,
-		.addr	= 0,
-		.pixfmt	= IPU_PIX_FMT_RGB24,
-		.detect	= detect_hdmi,
-		.enable	= enable_hdmi,
-		.mode	= {
-			.name		= "HDMI",
-			.refresh	= 60,
-			.xres		= 1024,
-			.yres		= 768,
-			.pixclock	= 15385,
-			.left_margin	= 220,
-			.right_margin	= 40,
-			.upper_margin	= 21,
-			.lower_margin	= 7,
-			.hsync_len	= 60,
-			.vsync_len	= 10,
-			.sync		= FB_SYNC_EXT,
-			.vmode		= FB_VMODE_NONINTERLACED
-		}
-	}
-};
-
-size_t display_count = ARRAY_SIZE(displays);
-
-static void setup_display(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	enable_ipu_clock();
-	imx_setup_hdmi();
-
-	/* Turn on LDB0,IPU,IPU DI0 clocks */
-	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
-
-	/* set LDB0, LDB1 clk select to 011/011 */
-	clrsetbits_le32(&mxc_ccm->cs2cdr,
-			MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
-			MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
-			(3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
-			(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
-
-	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
-
-	setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
-		     MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-
-	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
-	       IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
-	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
-	       IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
-	       IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
-	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
-	       IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
-	       IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
-	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
-	       &iomux->gpr[2]);
-
-	clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
-			IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
-			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
-}
-#endif
-
 int board_early_init_f(void)
 {
 #if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
+	setup_display_clock();
 #endif
 
 	return 0;
diff --git a/board/kosagi/novena/novena.h b/board/kosagi/novena/novena.h
index 6613ad469fb..244004d6942 100644
--- a/board/kosagi/novena/novena.h
+++ b/board/kosagi/novena/novena.h
@@ -20,4 +20,6 @@
 #define NOVENA_SD_CD			IMX_GPIO_NR(1, 4)
 #define NOVENA_SD_WP			IMX_GPIO_NR(1, 2)
 
+void setup_display_clock(void);
+
 #endif	/* __BOARD_KOSAGI_NOVENA_NOVENA_H__ */
diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c
new file mode 100644
index 00000000000..fdcd100e43d
--- /dev/null
+++ b/board/kosagi/novena/video.c
@@ -0,0 +1,102 @@
+/*
+ * Novena video output support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <stdio_dev.h>
+
+#include "novena.h"
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {
+	{
+		/* HDMI Output */
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB24,
+		.detect	= detect_hdmi,
+		.enable	= enable_hdmi,
+		.mode	= {
+			.name		= "HDMI",
+			.refresh	= 60,
+			.xres		= 1024,
+			.yres		= 768,
+			.pixclock	= 15384,
+			.left_margin	= 220,
+			.right_margin	= 40,
+			.upper_margin	= 21,
+			.lower_margin	= 7,
+			.hsync_len	= 60,
+			.vsync_len	= 10,
+			.sync		= FB_SYNC_EXT,
+			.vmode		= FB_VMODE_NONINTERLACED
+		},
+	},
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+void setup_display_clock(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+			MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
+			(3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+			(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
+
+	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+	setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
+		     MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+
+	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+	       IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
+	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+	       IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+	       IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+	       IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+	       IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
+	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+	       &iomux->gpr[2]);
+
+	clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
+			IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+}