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authorStefan Reinauer <reinauer@chromium.org>2011-12-14 13:33:26 -0800
committerStefan Reinauer <reinauer@chromium.org>2011-12-14 14:24:43 -0800
commit9c8b33f274189ddcac7f33db2d7c4e87ba7f7e33 (patch)
tree92dfae28c8552340fa57f9bc2b2d200db7f03388 /board/karo/tx25
parent776e37efbbb881930332b06cd7e8b44551fda3f7 (diff)
Move RW section of on Sandybridge to lower 4MB of the flash chip
H2C splits the flash device in 2 equal partitions of 4MB each. In order to avoid having to adapt user space tools to coreboot, change the flash map on Sandybridge to have the following flash layout: 1.5MB SI_ (ME) sections 2.5MB RW sections 4.0MB RO sections BUG=none TEST=boot tested on Stumpy Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: Ida0864389644b07b2d284770be62447547fdfb2e Reviewed-on: https://gerrit.chromium.org/gerrit/12937 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org>
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