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authorBin Meng <bmeng.cn@gmail.com>2016-02-17 00:16:25 -0800
committerBin Meng <bmeng.cn@gmail.com>2016-02-21 13:42:52 +0800
commita2e3b05e16c96ccc5929d60457938cd96912d758 (patch)
tree507b98f4bdf64a0130bee108d6e9aff15b62dddd /board/intel
parent87077e97d1a72286871d03a6f06903245b9caacd (diff)
x86: Add Intel Cougar Canyon 2 board
This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'board/intel')
-rw-r--r--board/intel/Kconfig9
-rw-r--r--board/intel/cougarcanyon2/Kconfig25
-rw-r--r--board/intel/cougarcanyon2/MAINTAINERS6
-rw-r--r--board/intel/cougarcanyon2/Makefile7
-rw-r--r--board/intel/cougarcanyon2/cougarcanyon2.c58
-rw-r--r--board/intel/cougarcanyon2/start.S9
6 files changed, 114 insertions, 0 deletions
diff --git a/board/intel/Kconfig b/board/intel/Kconfig
index f7d71c3612a..4d341aa7991 100644
--- a/board/intel/Kconfig
+++ b/board/intel/Kconfig
@@ -18,6 +18,14 @@ config TARGET_BAYLEYBAY
4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
PCIe and some other sensor interfaces.
+config TARGET_COUGARCANYON2
+ bool "Cougar Canyon 2"
+ help
+ This is the Intel Cougar Canyon 2 Customer Reference Board. It
+ is built on the Chief River platform with Intel Ivybridge Processor
+ and Panther Point chipset. The board has 4GB RAM, with some other
+ peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
+
config TARGET_CROWNBAY
bool "Crown Bay"
help
@@ -54,6 +62,7 @@ config TARGET_MINNOWMAX
endchoice
source "board/intel/bayleybay/Kconfig"
+source "board/intel/cougarcanyon2/Kconfig"
source "board/intel/crownbay/Kconfig"
source "board/intel/galileo/Kconfig"
source "board/intel/minnowmax/Kconfig"
diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig
new file mode 100644
index 00000000000..95a617b7256
--- /dev/null
+++ b/board/intel/cougarcanyon2/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_COUGARCANYON2
+
+config SYS_BOARD
+ default "cougarcanyon2"
+
+config SYS_VENDOR
+ default "intel"
+
+config SYS_SOC
+ default "ivybridge"
+
+config SYS_CONFIG_NAME
+ default "cougarcanyon2"
+
+config SYS_TEXT_BASE
+ default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_RESET_VECTOR
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select HAVE_FSP
+ select BOARD_ROMSIZE_KB_2048
+
+endif
diff --git a/board/intel/cougarcanyon2/MAINTAINERS b/board/intel/cougarcanyon2/MAINTAINERS
new file mode 100644
index 00000000000..a486739b5ee
--- /dev/null
+++ b/board/intel/cougarcanyon2/MAINTAINERS
@@ -0,0 +1,6 @@
+INTEL COUGAR CANYON 2 BOARD
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+F: board/intel/cougarcanyon2/
+F: include/configs/cougarcanyon2.h
+F: configs/cougarcanyon2_defconfig
diff --git a/board/intel/cougarcanyon2/Makefile b/board/intel/cougarcanyon2/Makefile
new file mode 100644
index 00000000000..abd924c6b32
--- /dev/null
+++ b/board/intel/cougarcanyon2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cougarcanyon2.o start.o
diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c
new file mode 100644
index 00000000000..31a480a6158
--- /dev/null
+++ b/board/intel/cougarcanyon2/cougarcanyon2.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <pci.h>
+#include <smsc_sio1007.h>
+#include <asm/ibmpc.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+#define SIO1007_RUNTIME_IOPORT 0x180
+
+int board_early_init_f(void)
+{
+ struct udevice *pch;
+ int ret;
+
+ ret = uclass_first_device(UCLASS_PCH, &pch);
+ if (ret)
+ return ret;
+ if (!pch)
+ return -ENODEV;
+
+ /* Initialize LPC interface to turn on superio chipset decode range */
+ dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE);
+ dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
+ dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
+ (SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
+ dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
+ SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
+
+ /* Enable legacy serial port at 0x3f8 */
+ sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
+
+ /* Enable SIO1007 runtime I/O port at 0x180 */
+ sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
+
+ /*
+ * On Cougar Canyon 2 board, the RS232 transiver connected to serial
+ * port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
+ * Set the pin value to 1 to enable the RS232 transiver.
+ */
+ sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
+ GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
+ sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
+
+ return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
diff --git a/board/intel/cougarcanyon2/start.S b/board/intel/cougarcanyon2/start.S
new file mode 100644
index 00000000000..d8f227c706b
--- /dev/null
+++ b/board/intel/cougarcanyon2/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+ jmp early_board_init_ret