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authorWolfgang Denk <wd@pollux.(none)>2005-09-25 16:22:14 +0200
committerWolfgang Denk <wd@pollux.(none)>2005-09-25 16:22:14 +0200
commit0148e8cb4337a2c65a5ed539d0e7b87f2e099329 (patch)
tree91341269c2eb3bd6356e608d8f9a5b910180fe2e /board/integratorap
parent389db1f113cbc0f81f2a7311fa4114c749c81595 (diff)
Update multicore CM9XX support for Integrator AP to allow booting from flash
Patch by Jean-Paul Saman, 8 Feb 2005
Diffstat (limited to 'board/integratorap')
-rw-r--r--board/integratorap/integratorap.c37
-rw-r--r--board/integratorap/platform.S183
2 files changed, 213 insertions, 7 deletions
diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c
index 31bd1d48eb5..ff074ca3bcc 100644
--- a/board/integratorap/integratorap.c
+++ b/board/integratorap/integratorap.c
@@ -75,6 +75,11 @@ int board_init (void)
gd->flags = 0;
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+ cm_remap(); /* remaps writeable memory to 0x00000000 */
+#endif
+
icache_enable ();
flash__init ();
@@ -475,6 +480,38 @@ void ether__init (void)
******************************/
int dram_init (void)
{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_CM_SPD_DETECT
+ {
+extern void dram_query(void);
+ unsigned long cm_reg_sdram;
+ unsigned long sdram_shift;
+
+ dram_query(); /* Assembler accesses to CM registers */
+ /* Queries the SPD values */
+
+ /* Obtain the SDRAM size from the CM SDRAM register */
+
+ cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+ /* Register SDRAM size
+ *
+ * 0xXXXXXXbbb000bb 16 MB
+ * 0xXXXXXXbbb001bb 32 MB
+ * 0xXXXXXXbbb010bb 64 MB
+ * 0xXXXXXXbbb011bb 128 MB
+ * 0xXXXXXXbbb100bb 256 MB
+ *
+ */
+ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
+ gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
+
+ }
+#endif /* CM_SPD_DETECT */
+
return 0;
}
diff --git a/board/integratorap/platform.S b/board/integratorap/platform.S
index 897c7bbc616..fefee72f3e7 100644
--- a/board/integratorap/platform.S
+++ b/board/integratorap/platform.S
@@ -14,7 +14,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -26,12 +26,6 @@
#include <config.h>
#include <version.h>
-.globl platformsetup
-platformsetup:
-
- /* All done by Integrator's boot monitor! */
- mov pc, lr
-
/* Reset using CM control register */
.global reset_cpu
reset_cpu:
@@ -42,3 +36,178 @@ reset_cpu:
reset_failed:
b reset_failed
+
+/* set up the platform, once the cpu has been initialized */
+.globl platformsetup
+platformsetup:
+ /* If U-Boot has been run after the ARM boot monitor
+ * then all the necessary actions have been done
+ * otherwise we are running from user flash mapped to 0x00000000
+ * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
+ * Changes to the (possibly soft) reset defaults of the processor
+ * itself should be performed in cpu/arm<>/start.S
+ * This function affects only the core module or board settings
+ */
+
+#ifdef CONFIG_CM_INIT
+ /* CM has an initialization register
+ * - bits in it are wired into test-chip pins to force
+ * reset defaults
+ * - may need to change its contents for U-Boot
+ */
+
+ /* set the desired CM specific value */
+ mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+ orr r2,r2,#CMMASK_INIT_102
+#else
+
+#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
+ !defined (CONFIG_CM940T)
+
+#ifdef CONFIG_CM_MULTIPLE_SSRAM
+ /* set simple mapping */
+ and r2,r2,#CMMASK_MAP_SIMPLE
+#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
+
+#ifdef CONFIG_CM_TCRAM
+ /* disable TCRAM */
+ and r2,r2,#CMMASK_TCRAM_DISABLE
+#endif /* #ifdef CONFIG_CM_TCRAM */
+
+#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
+ defined (CONFIG_CM1136JF_S)
+
+ and r2,r2,#CMMASK_LE
+
+#endif /* cpu with little endian initialization */
+
+ orr r2,r2,#CMMASK_CMxx6_COMMON
+
+#endif /* CMxx6 code */
+
+#endif /* ARM102xxE value */
+
+ /* read CM_INIT */
+ mov r0, #CM_BASE
+ ldr r1, [r0, #OS_INIT]
+ /* check against desired bit setting */
+ and r3,r1,r2
+ cmp r3,r2
+ beq init_reg_OK
+
+ /* lock for change */
+ mov r3, #CMVAL_LOCK
+ and r3,r3,#CMMASK_LOCK
+ str r3, [r0, #OS_LOCK]
+ /* set desired value */
+ orr r1,r1,r2
+ /* write & relock CM_INIT */
+ str r1, [r0, #OS_INIT]
+ mov r1, #CMVAL_UNLOCK
+ str r1, [r0, #OS_LOCK]
+
+ /* soft reset so new values used */
+ b reset_cpu
+
+init_reg_OK:
+
+#endif /* CONFIG_CM_INIT */
+
+ mov pc, lr
+
+#ifdef CONFIG_CM_SPD_DETECT
+ /* Fast memory is available for the DRAM data
+ * - ensure it has been transferred, then summarize the data
+ * into a CM register
+ */
+.globl dram_query
+dram_query:
+ stmfd r13!,{r4-r6,lr}
+ /* set up SDRAM info */
+ /* - based on example code from the CM User Guide */
+ mov r0, #CM_BASE
+
+readspdbit:
+ ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
+ and r1, r1, #0x20 /* mask SPD bit (5) */
+ cmp r1, #0x20 /* test if set */
+ bne readspdbit
+
+setupsdram:
+ add r0, r0, #OS_SPD /* address the copy of the SDP data */
+ ldrb r1, [r0, #3] /* number of row address lines */
+ ldrb r2, [r0, #4] /* number of column address lines */
+ ldrb r3, [r0, #5] /* number of banks */
+ ldrb r4, [r0, #31] /* module bank density */
+ mul r5, r4, r3 /* size of SDRAM (MB divided by 4) */
+ mov r5, r5, ASL#2 /* size in MB */
+ mov r0, #CM_BASE /* reload for later code */
+ cmp r5, #0x10 /* is it 16MB? */
+ bne not16
+ mov r6, #0x2 /* store size and CAS latency of 2 */
+ b writesize
+
+not16:
+ cmp r5, #0x20 /* is it 32MB? */
+ bne not32
+ mov r6, #0x6
+ b writesize
+
+not32:
+ cmp r5, #0x40 /* is it 64MB? */
+ bne not64
+ mov r6, #0xa
+ b writesize
+
+not64:
+ cmp r5, #0x80 /* is it 128MB? */
+ bne not128
+ mov r6, #0xe
+ b writesize
+
+not128:
+ /* if it is none of these sizes then it is either 256MB, or
+ * there is no SDRAM fitted so default to 256MB
+ */
+ mov r6, #0x12
+
+writesize:
+ mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
+ orr r2, r1, r2, ASL#12 /* OR in column address lines */
+ orr r3, r2, r3, ASL#16 /* OR in number of banks */
+ orr r6, r6, r3 /* OR in size and CAS latency */
+ str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
+
+#endif /* #ifdef CONFIG_CM_SPD_DETECT */
+
+ ldmfd r13!,{r4-r6,pc} /* back to caller */
+
+#ifdef CONFIG_CM_REMAP
+ /* CM remap bit is operational
+ * - use it to map writeable memory at 0x00000000, in place of flash
+ */
+.globl cm_remap
+cm_remap:
+ stmfd r13!,{r4-r10,lr}
+
+ mov r0, #CM_BASE
+ ldr r1, [r0, #OS_CTRL]
+ orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
+ str r1, [r0, #OS_CTRL]
+
+ /* Now 0x00000000 is writeable, replace the vectors */
+ ldr r0, =_start /* r0 <- start of vectors */
+ ldr r2, =_armboot_start /* r2 <- past vectors */
+ sub r1,r1,r1 /* destination 0x00000000 */
+
+copy_vec:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ ble copy_vec
+
+ ldmfd r13!,{r4-r10,pc} /* back to caller */
+
+#endif /* #ifdef CONFIG_CM_REMAP */