diff options
author | Scott Sweeny <scott.sweeny@timesys.com> | 2009-04-29 11:19:44 -0400 |
---|---|---|
committer | Scott Sweeny <scott.sweeny@timesys.com> | 2009-04-29 11:19:44 -0400 |
commit | 1f6422345c3594647eb16e33194be62906dbdc22 (patch) | |
tree | a1b5a9cb51216df1b6ccdd434bfef6788627ed28 /board/inka4x0/mt48lc16m16a2-75.h | |
parent | e6b6d16de73de6a76e2ec4338291e828b860f040 (diff) |
Add support for OMAP3430 Labrador
This patch originally from LogicPD OMAP35x Release 1.5.0
Original Patch Name: u-boot-1.1.4-omap3430-labrador.patch
Diffstat (limited to 'board/inka4x0/mt48lc16m16a2-75.h')
-rw-r--r-- | board/inka4x0/mt48lc16m16a2-75.h | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h deleted file mode 100644 index 13a97ac462..0000000000 --- a/board/inka4x0/mt48lc16m16a2-75.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define SDRAM_DDR 1 /* is SDR */ - -#if defined(CONFIG_MPC5200) -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ -/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ -#define SDRAM_CONFIG2 0x8AD70000 -/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif |