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authorKever Yang <kever.yang@rock-chips.com>2019-07-22 20:02:12 +0800
committerKever Yang <kever.yang@rock-chips.com>2019-07-29 10:26:41 +0800
commitb678f2790c8634539a3458f03d53f2273e0fdc75 (patch)
treef22c1322b9a034c6a031e6d44277b5d49828fd78 /board/google
parent0221910042a629e3439576e8807f04b612c94fd5 (diff)
rockchip: rk3288: Move veyron_init() back to veyron.c
The veyron_init() should go to its board file veyron.c, and the board_early_init_f() could be the right place. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'board/google')
-rw-r--r--board/google/veyron/veyron.c63
1 files changed, 63 insertions, 0 deletions
diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
index 361f0e9da2..dd2c014c60 100644
--- a/board/google/veyron/veyron.c
+++ b/board/google/veyron/veyron.c
@@ -3,20 +3,82 @@
* (C) Copyright 2015 Google, Inc
*/
+#include <clk.h>
#include <common.h>
+#include <dm.h>
#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <power/regulator.h>
/*
* We should increase the DDR voltage to 1.2V using the PWM regulator.
* There is a U-Boot driver for this but it may need to add support for the
* 'voltage-table' property.
*/
+#ifndef CONFIG_SPL_BUILD
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+static int veyron_init(void)
+{
+ struct udevice *dev;
+ struct clk clk;
+ int ret;
+
+ ret = regulator_get_by_platname("vdd_arm", &dev);
+ if (ret) {
+ debug("Cannot set regulator name\n");
+ return ret;
+ }
+
+ /* Slowly raise to max CPU voltage to prevent overshoot */
+ ret = regulator_set_value(dev, 1200000);
+ if (ret)
+ return ret;
+ udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+ ret = regulator_set_value(dev, 1400000);
+ if (ret)
+ return ret;
+ udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+ ret = rockchip_get_clk(&clk.dev);
+ if (ret)
+ return ret;
+ clk.id = PLL_APLL;
+ ret = clk_set_rate(&clk, 1800000000);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+
+ ret = regulator_get_by_platname("vcc33_sd", &dev);
+ if (ret) {
+ debug("Cannot get regulator name\n");
+ return ret;
+ }
+
+ ret = regulator_set_value(dev, 3300000);
+ if (ret)
+ return ret;
+
+ ret = regulators_enable_boot_on(false);
+ if (ret) {
+ debug("%s: Cannot enable boot on regulators\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+#endif
int board_early_init_f(void)
{
struct udevice *dev;
int ret;
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+ if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+ ret = veyron_init();
+ if (ret)
+ return ret;
+ }
+#endif
/*
* This init is done in SPL, but when chain-loading U-Boot SPL will
* have been skipped. Allow the clock driver to check if it needs
@@ -30,3 +92,4 @@ int board_early_init_f(void)
return 0;
}
+#endif