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authorFabio Estevam <fabio.estevam@freescale.com>2012-06-19 07:24:56 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:29 +0200
commitf69b0653acf5482a94fa1ec9542165914e30e50c (patch)
tree1e7f8cf6da1676805b3918be7673e39bd7ef8f8b /board/freescale
parente3ddc646031551627c4eeae4598f8862251a3f94 (diff)
mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
commit acc4959fc1 (Revert "i.MX28: Enable additional DRAM address bits") broke mx28evk boot. Fix it by properly adjusting the HW_DRAM_CTL29 register value. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/mx28evk/iomux.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c
index 6587c454fe7..00cc0cc2fa2 100644
--- a/board/freescale/mx28evk/iomux.c
+++ b/board/freescale/mx28evk/iomux.c
@@ -161,6 +161,20 @@ const iomux_cfg_t iomux_setup[] = {
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
};
+#define HW_DRAM_CTL29 (0x74 >> 2)
+#define CS_MAP 0xf
+#define COLUMN_SIZE 0x2
+#define ADDR_PINS 0x1
+#define APREBIT 0xa
+
+#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
+ ADDR_PINS << 8 | APREBIT)
+
+void mx28_adjust_memory_params(uint32_t *dram_vals)
+{
+ dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
+}
+
void board_init_ll(void)
{
mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));