diff options
| author | Ye Li <ye.li@nxp.com> | 2020-11-05 22:05:21 -0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2020-11-08 18:37:00 -0800 |
| commit | 5d556b8e214739deb5c3c71efa2ea8fc28f2a643 (patch) | |
| tree | 8011bd910c57087ae3c2090b3f1348fb30a5fb40 /board/freescale | |
| parent | 501690cb93c4df30700c1bf40f0f2eaed2444503 (diff) | |
MLK-24971-1 imx8mp_evk: Change to nominal voltage on DDR4 EVK
Because DDR4 runs at 3200MTS, this speed does not require to use overdrive
voltage for VDD_SOC, so set VDD_SOC to nominal 0.85v on DDR4 EVK.
The VDD_ARM was set to 0.95v to avoid timing risk from SOC to ARM when
VDD_SOC is 0.95v, set it back to 0.85v as well.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/imx8mp_evk/spl.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index 84b36786bad..4cb6385bc47 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -187,6 +187,7 @@ int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); +#ifdef CONFIG_IMX8M_LPDDR4 /* * increase VDD_SOC to typical value 0.95V before first * DRAM access, set DVS1 to 0.85v for suspend. @@ -200,8 +201,10 @@ int power_init_board(void) /* Kernel uses OD/OD freq for SOC */ /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); +#elif defined(CONFIG_IMX8M_DDR4) + /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */ + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); -#ifdef CONFIG_IMX8M_DDR4 /* Set NVCC_DRAM to 1.2v for DDR4 */ pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18); #endif |