diff options
author | Tom Rini <trini@konsulko.com> | 2021-09-09 07:54:53 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2021-10-01 21:08:19 -0400 |
commit | fae2ea5951a53031bfe057d35967c01077dafd8c (patch) | |
tree | 66c99d616cb75181ef40a1dd2c32f5d5600d2841 /board/freescale | |
parent | 4987658be57fde01800fc42d15256890763c8e20 (diff) |
ppc: Remove MPC8349EMDS board and ARCH_MPC8349 support
This board has not been converted to CONFIG_DM by the deadline.
Remove it.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'board/freescale')
-rw-r--r-- | board/freescale/mpc8349emds/Kconfig | 25 | ||||
-rw-r--r-- | board/freescale/mpc8349emds/MAINTAINERS | 9 | ||||
-rw-r--r-- | board/freescale/mpc8349emds/Makefile | 8 | ||||
-rw-r--r-- | board/freescale/mpc8349emds/ddr.c | 100 | ||||
-rw-r--r-- | board/freescale/mpc8349emds/mpc8349emds.c | 277 | ||||
-rw-r--r-- | board/freescale/mpc8349emds/pci.c | 118 |
6 files changed, 0 insertions, 537 deletions
diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig deleted file mode 100644 index d1541180799..00000000000 --- a/board/freescale/mpc8349emds/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if TARGET_MPC8349EMDS - -config SYS_BOARD - default "mpc8349emds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8349EMDS" - -endif - -if TARGET_MPC8349EMDS_SDRAM - -config SYS_BOARD - default "mpc8349emds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8349EMDS_SDRAM" - -endif diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS deleted file mode 100644 index a8f26a9a316..00000000000 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -MPC8349EMDS BOARD -#M: Kim Phillips <kim.phillips@freescale.com> -S: Orphan (since 2018-05) -F: board/freescale/mpc8349emds/ -F: include/configs/MPC8349EMDS.h -F: configs/MPC8349EMDS_defconfig -F: configs/MPC8349EMDS_SDRAM_defconfig -F: configs/MPC8349EMDS_PCI64_defconfig -F: configs/MPC8349EMDS_SLAVE_defconfig diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile deleted file mode 100644 index af02f65cb00..00000000000 --- a/board/freescale/mpc8349emds/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8349emds.o -obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c deleted file mode 100644 index ac5ddc6d94b..00000000000 --- a/board/freescale/mpc8349emds/ddr.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> - -#include <fsl_ddr_sdram.h> -#include <fsl_ddr_dimm_params.h> - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {2, 300, 4, 4, 2, 0}, - {2, 365, 4, 6, 2, 0}, - {2, 450, 4, 7, 2, 0}, - {2, 850, 4, 31, 2, 0}, - {1, 300, 4, 4, 2, 0}, - {1, 365, 4, 6, 2, 0}, - {1, 450, 4, 7, 2, 0}, - {1, 850, 4, 31, 2, 0}, - {} -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - unsigned int i; - ulong ddr_freq; - - if (ctrl_num != 0) /* we have only one controller */ - return; - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (pdimm[i].n_ranks) - break; - } - if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ - return; - - pbsp = udimm0; - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm[i].n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } - -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - popts->dqs_config = 0; /* only true DQS signal is used on board */ -} diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c deleted file mode 100644 index eff248104dc..00000000000 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ /dev/null @@ -1,277 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <fdt_support.h> -#include <init.h> -#include <ioports.h> -#include <mpc83xx.h> -#include <asm/bitops.h> -#include <asm/global_data.h> -#include <asm/mpc8349_pci.h> -#include <i2c.h> -#include <spi.h> -#include <miiphy.h> -#ifdef CONFIG_SYS_FSL_DDR2 -#include <fsl_ddr_sdram.h> -#else -#include <spd_sdram.h> -#endif -#include <linux/delay.h> - -#if defined(CONFIG_OF_LIBFDT) -#include <linux/libfdt.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int fixed_sdram(void); -void sdram_init(void); - -#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx) -void ddr_enable_ecc(unsigned int dram_size); -#endif - -int board_early_init_f (void) -{ - volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR; - - /* Enable flash write */ - bcsr[1] &= ~0x01; - -#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY - /* Use USB PHY on SYS board */ - bcsr[5] |= 0x02; -#endif - - return 0; -} - -int dram_init(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - phys_size_t msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) - return -ENXIO; - - /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; -#if defined(CONFIG_SPD_EEPROM) -#ifndef CONFIG_SYS_FSL_DDR2 - msize = spd_sdram() * 1024 * 1024; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - ddr_enable_ecc(msize); -#endif -#else - msize = fsl_ddr_sdram(); -#endif -#else - msize = fixed_sdram() * 1024 * 1024; -#endif - /* - * Initialize SDRAM if it is on local bus. - */ - sdram_init(); - - /* set total bus SDRAM size(bytes) -- DDR */ - gd->ram_size = msize; - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - ************************************************************************/ -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_DDR_SIZE; - u32 ddr_size = msize << 20; /* DDR size in bytes */ - u32 ddr_size_log2 = __ilog2(ddr_size); - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - -#if (CONFIG_SYS_DDR_SIZE != 256) -#warning Currenly any ddr size other than 256 is not supported -#endif -#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0) -#warning Chip select bounds is only configurable in 16MB increments -#endif - im->ddr.csbnds[2].csbnds = - ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | - (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >> - CSBNDS_EA_SHIFT) & CSBNDS_EA); - im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; - - /* currently we use only one CS, so disable the other banks */ - im->ddr.cs_config[0] = 0; - im->ddr.cs_config[1] = 0; - im->ddr.cs_config[3] = 0; - - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - - im->ddr.sdram_cfg = - SDRAM_CFG_SREN - | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - udelay(200); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - return msize; -} -#endif/*!CONFIG_SYS_SPD_EEPROM*/ - - -int checkboard (void) -{ - /* - * Warning: do not read the BCSR registers here - * - * There is a timing bug in the 8349E and 8349EA BCSR code - * version 1.2 (read from BCSR 11) that will cause the CFI - * flash initialization code to overwrite BCSR 0, disabling - * the serial ports and gigabit ethernet - */ - - puts("Board: Freescale MPC8349EMDS\n"); - return 0; -} - -/* - * if MPC8349EMDS is soldered with SDRAM - */ -#if defined(CONFIG_SYS_BR2_PRELIM) \ - && defined(CONFIG_SYS_OR2_PRELIM) \ - && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ - && defined(CONFIG_SYS_LBLAWAR2_PRELIM) -/* - * Initialize SDRAM memory on the Local Bus. - */ - -void sdram_init(void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbc_t *lbc = &immap->im_lbc; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 | - LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 | - LSDMR_WRC3 | LSDMR_CL3; - /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c - */ - - /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = 0x00000000; - /* LB refresh timer prescal, 266MHz/32 */ - lbc->mrtpr = 0x20000000; - /* LB sdram refresh timer, about 6us */ - lbc->lsrt = 0x32000000; - asm("sync"); - - /* - * Configure the SDRAM controller Machine Mode Register. - */ - - /* 0x40636733; normal operation */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - - /* 0x68636733; precharge all the banks */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* 0x48636733; auto refresh */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; - asm("sync"); - /*1 times*/ - *sdram_addr = 0xff; - udelay(100); - /*2 times*/ - *sdram_addr = 0xff; - udelay(100); - /*3 times*/ - *sdram_addr = 0xff; - udelay(100); - /*4 times*/ - *sdram_addr = 0xff; - udelay(100); - /*5 times*/ - *sdram_addr = 0xff; - udelay(100); - /*6 times*/ - *sdram_addr = 0xff; - udelay(100); - /*7 times*/ - *sdram_addr = 0xff; - udelay(100); - /*8 times*/ - *sdram_addr = 0xff; - udelay(100); - - /* 0x58636733; mode register write operation */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); - - /* 0x40636733; normal operation */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; - asm("sync"); - *sdram_addr = 0xff; - udelay(100); -} -#else -void sdram_init(void) -{ -} -#endif - -/* - * The following are used to control the SPI chip selects for the SPI command. - */ -#ifdef CONFIG_MPC8XXX_SPI - -#define SPI_CS_MASK 0x80000000 - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat &= ~SPI_CS_MASK; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; - - iopd->dat |= SPI_CS_MASK; -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c deleted file mode 100644 index 8c76c46d420..00000000000 --- a/board/freescale/mpc8349emds/pci.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include <init.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <common.h> -#include <mpc83xx.h> -#include <pci.h> -#include <i2c.h> -#include <asm/fsl_i2c.h> -#include <linux/delay.h> - -static struct pci_region pci1_regions[] = { - { - bus_start: CONFIG_SYS_PCI1_MEM_BASE, - phys_start: CONFIG_SYS_PCI1_MEM_PHYS, - size: CONFIG_SYS_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI1_IO_BASE, - phys_start: CONFIG_SYS_PCI1_IO_PHYS, - size: CONFIG_SYS_PCI1_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI1_MMIO_BASE, - phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, - size: CONFIG_SYS_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; - -#ifdef CONFIG_MPC83XX_PCI2 -static struct pci_region pci2_regions[] = { - { - bus_start: CONFIG_SYS_PCI2_MEM_BASE, - phys_start: CONFIG_SYS_PCI2_MEM_PHYS, - size: CONFIG_SYS_PCI2_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI2_IO_BASE, - phys_start: CONFIG_SYS_PCI2_IO_PHYS, - size: CONFIG_SYS_PCI2_IO_SIZE, - flags: PCI_REGION_IO - }, - { - bus_start: CONFIG_SYS_PCI2_MMIO_BASE, - phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, - size: CONFIG_SYS_PCI2_MMIO_SIZE, - flags: PCI_REGION_MEM - }, -}; -#endif - -#ifndef CONFIG_PCISLAVE -void pib_init(void) -{ - u8 val8, orig_i2c_bus; - /* - * Assign PIB PMC slot to desired PCI bus - */ - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); -#if defined(CONFIG_PCI_64BIT) - val8 = 0xf4; /* PMC2:PCI1/64-bit */ -#elif defined(CONFIG_PCI_ALL_PCI1) - val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ -#elif defined(CONFIG_PCI_ONE_PCI1) - val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ -#else - val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ -#endif - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - asm("eieio"); - -#if defined(CONFIG_PCI_64BIT) - printf("PCI1: 64-bit on PMC2\n"); -#elif defined(CONFIG_PCI_ALL_PCI1) - printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); -#elif defined(CONFIG_PCI_ONE_PCI1) - printf("PCI1: 32-bit on PMC1\n"); - printf("PCI2: 32-bit on PMC2, PMC3\n"); -#else - printf("PCI1: 32-bit on PMC1, PMC2\n"); - printf("PCI2: 32-bit on PMC3\n"); -#endif - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); -} - -#endif /* CONFIG_PCISLAVE */ |