diff options
author | Stefan Agner <stefan.agner@toradex.com> | 2014-07-17 16:28:37 +0200 |
---|---|---|
committer | Stefan Agner <stefan.agner@toradex.com> | 2014-10-23 11:10:58 +0200 |
commit | af7c111153cbe14f763bea89b7db60cac710bcbe (patch) | |
tree | 5157fac022194c543c4f222033f66ee64713d222 /board/freescale | |
parent | b16eb3e299d15577c18531223ff91ae225d21b4b (diff) |
vf610: enable external 32KHz oscillator
Enable the SCSC (Slow Clock Source Controller) and select the
external 32KHz oscillator. This improves accuracy of the RTC.
Diffstat (limited to 'board/freescale')
-rw-r--r-- | board/freescale/vf610twr/vf610twr.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 6b03495febf..085c2ee790f 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -175,7 +175,7 @@ static void clock_init(void) CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | CCM_CCGR2_QSPI0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, - CCM_CCGR3_ANADIG_CTRL_MASK); + CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); @@ -256,9 +256,20 @@ int board_early_init_f(void) int board_init(void) { + struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* + * Enable external 32K Oscillator + * + * The internal clock experiences significant drift + * so we must use the external oscillator in order + * to maintain correct time in the hwclock + */ + setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); + return 0; } |