diff options
author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2014-10-14 15:39:27 +0200 |
---|---|---|
committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2014-10-14 15:39:27 +0200 |
commit | 4181f1b45cdbac89f2f626a50ce59aa9c4fdf8dd (patch) | |
tree | 3bb7b8623e3caeaa0153b18bd8c9a5594330d4f9 /board/freescale | |
parent | 673ed5cf1f142b0e01959fa1e086ec7fdec4a9ae (diff) | |
parent | c43fd23cf619856b0763a64a6a3bcf3663058c49 (diff) |
Merge tag 'v2014.10' into 2014.10-toradex-next
Prepare v2014.10
Diffstat (limited to 'board/freescale')
-rw-r--r-- | board/freescale/mx6qarm2/MAINTAINERS | 4 | ||||
-rw-r--r-- | board/freescale/mx6qarm2/imximage.cfg | 189 | ||||
-rw-r--r-- | board/freescale/mx6qarm2/imximage_mx6dl.cfg | 462 | ||||
-rw-r--r-- | board/freescale/mx6qarm2/mx6qarm2.c | 11 | ||||
-rw-r--r-- | board/freescale/mx6qsabreauto/mx6qsabreauto.c | 16 | ||||
-rw-r--r-- | board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg (renamed from board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg) | 0 | ||||
-rw-r--r-- | board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 | ||||
-rw-r--r-- | board/freescale/vf610twr/MAINTAINERS | 1 | ||||
-rw-r--r-- | board/freescale/vf610twr/vf610twr.c | 141 |
9 files changed, 773 insertions, 53 deletions
diff --git a/board/freescale/mx6qarm2/MAINTAINERS b/board/freescale/mx6qarm2/MAINTAINERS index 42c19d13ec..52cf7f935a 100644 --- a/board/freescale/mx6qarm2/MAINTAINERS +++ b/board/freescale/mx6qarm2/MAINTAINERS @@ -1,6 +1,10 @@ MX6QARM2 BOARD M: Jason Liu <r64343@freescale.com> +M: Ye Li <b37916@freescale.com> S: Maintained F: board/freescale/mx6qarm2/ F: include/configs/mx6qarm2.h F: configs/mx6qarm2_defconfig +F: configs/mx6dlarm2_defconfig +F: configs/mx6qarm2_lpddr2_defconfig +F: configs/mx6dlarm2_lpddr2_defconfig diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index 710f34d9a5..c85bde510e 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. * Jason Liu <r64343@freescale.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -30,6 +30,185 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ +#ifdef CONFIG_MX6DQ_LPDDR2 +/* DCD */ +DATA 4 0x020C4018 0x60324 + +DATA 4 0x020E05a8 0x00003038 +DATA 4 0x020E05b0 0x00003038 +DATA 4 0x020E0524 0x00003038 +DATA 4 0x020E051c 0x00003038 + +DATA 4 0x020E0518 0x00003038 +DATA 4 0x020E050c 0x00003038 +DATA 4 0x020E05b8 0x00003038 +DATA 4 0x020E05c0 0x00003038 + +DATA 4 0x020E05ac 0x00000038 +DATA 4 0x020E05b4 0x00000038 +DATA 4 0x020E0528 0x00000038 +DATA 4 0x020E0520 0x00000038 + +DATA 4 0x020E0514 0x00000038 +DATA 4 0x020E0510 0x00000038 +DATA 4 0x020E05bc 0x00000038 +DATA 4 0x020E05c4 0x00000038 + +DATA 4 0x020E056c 0x00000038 +DATA 4 0x020E0578 0x00000038 +DATA 4 0x020E0588 0x00000038 +DATA 4 0x020E0594 0x00000038 + +DATA 4 0x020E057c 0x00000038 +DATA 4 0x020E0590 0x00000038 +DATA 4 0x020E0598 0x00000038 +DATA 4 0x020E058c 0x00000000 + +DATA 4 0x020E059c 0x00000038 +DATA 4 0x020E05a0 0x00000038 +DATA 4 0x020E0784 0x00000038 +DATA 4 0x020E0788 0x00000038 + +DATA 4 0x020E0794 0x00000038 +DATA 4 0x020E079c 0x00000038 +DATA 4 0x020E07a0 0x00000038 +DATA 4 0x020E07a4 0x00000038 + +DATA 4 0x020E07a8 0x00000038 +DATA 4 0x020E0748 0x00000038 +DATA 4 0x020E074c 0x00000038 +DATA 4 0x020E0750 0x00020000 + +DATA 4 0x020E0758 0x00000000 +DATA 4 0x020E0774 0x00020000 +DATA 4 0x020E078c 0x00000038 +DATA 4 0x020E0798 0x00080000 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b401c 0x00008000 + +DATA 4 0x021b085c 0x1b5f01ff +DATA 4 0x021b485c 0x1b5f01ff + +DATA 4 0x021b0800 0xa1390000 +DATA 4 0x021b4800 0xa1390000 + +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b4890 0x00400000 + +DATA 4 0x021b48bc 0x00055555 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b482c 0xf3333333 +DATA 4 0x021b4830 0xf3333333 +DATA 4 0x021b4834 0xf3333333 +DATA 4 0x021b4838 0xf3333333 + +DATA 4 0x021b0848 0x49383b39 +DATA 4 0x021b0850 0x30364738 +DATA 4 0x021b4848 0x3e3c3846 +DATA 4 0x021b4850 0x4c294b35 + +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x0 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x0 + +DATA 4 0x021b0858 0xf00 +DATA 4 0x021b4858 0xf00 + +DATA 4 0x021b08b8 0x800 +DATA 4 0x021b48b8 0x800 + +DATA 4 0x021b000c 0x555a61a5 +DATA 4 0x021b0004 0x20036 +DATA 4 0x021b0010 0x160e83 +DATA 4 0x021b0014 0xdd +DATA 4 0x021b0018 0x8174c +DATA 4 0x021b002c 0xf9f26d2 +DATA 4 0x021b0030 0x20e +DATA 4 0x021b0038 0x200aac +DATA 4 0x021b0008 0x0 + +DATA 4 0x021b0040 0x5f + +DATA 4 0x021b0000 0xc3010000 + +DATA 4 0x021b400c 0x555a61a5 +DATA 4 0x021b4004 0x20036 +DATA 4 0x021b4010 0x160e83 +DATA 4 0x021b4014 0xdd +DATA 4 0x021b4018 0x8174c +DATA 4 0x021b402c 0xf9f26d2 +DATA 4 0x021b4030 0x20e +DATA 4 0x021b4038 0x200aac +DATA 4 0x021b4008 0x0 + +DATA 4 0x021b4040 0x3f +DATA 4 0x021b4000 0xc3010000 + +DATA 4 0x021b001c 0x3f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0xc2018030 +DATA 4 0x021b001c 0x6028030 +DATA 4 0x021b001c 0x2038030 + +DATA 4 0x021b401c 0x3f8030 +DATA 4 0x021b401c 0xff0a8030 +DATA 4 0x021b401c 0xc2018030 +DATA 4 0x021b401c 0x6028030 +DATA 4 0x021b401c 0x2038030 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b4800 0xa1390003 + +DATA 4 0x021b0020 0x7800 +DATA 4 0x021b4020 0x7800 + +DATA 4 0x021b0818 0x0 +DATA 4 0x021b4818 0x0 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b4800 0xa1390003 + +DATA 4 0x021b08b8 0x800 +DATA 4 0x021b48b8 0x800 + +DATA 4 0x021b001c 0x0 +DATA 4 0x021b401c 0x0 + +DATA 4 0x021b0404 0x00011006 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +#else DATA 4 0x020e05a8 0x00000030 DATA 4 0x020e05b0 0x00000030 DATA 4 0x020e0524 0x00000030 @@ -142,12 +321,8 @@ DATA 4 0x021b48b8 0x00000800 DATA 4 0x021b001c 0x00000000 DATA 4 0x021b0404 0x00011006 -DATA 4 0x020e0010 0xF00000FF -DATA 4 0x020e0018 0x00070007 -DATA 4 0x020e001c 0x00070007 - DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 DATA 4 0x020c4078 0x00FFF300 @@ -159,3 +334,5 @@ DATA 4 0x020e0010 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F + +#endif /* CONFIG_MX6DQ_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg new file mode 100644 index 0000000000..ae8dcc626e --- /dev/null +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -0,0 +1,462 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Jason Liu <r64343@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + + + +#ifdef CONFIG_MX6DL_LPDDR2 + +/* IOMUX SETTINGS */ +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ +DATA 4 0x020E04bc 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ +DATA 4 0x020E04c0 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */ +DATA 4 0x020E04c4 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */ +DATA 4 0x020E04c8 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */ +DATA 4 0x020E04cc 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */ +DATA 4 0x020E04d0 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */ +DATA 4 0x020E04d4 0x00003028 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */ +DATA 4 0x020E04d8 0x00003028 + +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ +DATA 4 0x020E0470 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ +DATA 4 0x020E0474 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */ +DATA 4 0x020E0478 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */ +DATA 4 0x020E047c 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */ +DATA 4 0x020E0480 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */ +DATA 4 0x020E0484 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */ +DATA 4 0x020E0488 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */ +DATA 4 0x020E048c 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ +DATA 4 0x020E0464 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ +DATA 4 0x020E0490 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ +DATA 4 0x020E04ac 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */ +DATA 4 0x020E04b0 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ +DATA 4 0x020E0494 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */ +DATA 4 0x020E04a4 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */ +DATA 4 0x020E04a8 0x00000038 +/* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 + * DSE can be configured using Group Control Register: + * IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ +DATA 4 0x020E04a0 0x00000000 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ +DATA 4 0x020E04b4 0x00000038 +/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ +DATA 4 0x020E04b8 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B0DS */ +DATA 4 0x020E0764 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B1DS */ +DATA 4 0x020E0770 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B2DS */ +DATA 4 0x020E0778 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B3DS */ +DATA 4 0x020E077c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B4DS */ +DATA 4 0x020E0780 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B5DS */ +DATA 4 0x020E0784 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B6DS */ +DATA 4 0x020E078c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_B7DS */ +DATA 4 0x020E0748 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ +DATA 4 0x020E074c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ +DATA 4 0x020E076c 0x00000038 +/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ +DATA 4 0x020E0750 0x00020000 +/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ +DATA 4 0x020E0754 0x00000000 +/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ +DATA 4 0x020E0760 0x00020000 +/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ +DATA 4 0x020E0774 0x00080000 + +/* + * DDR Controller Registers + * + * Manufacturer: Mocron + * Device Part Number: MT42L64M64D2KH-18 + * Clock Freq.: 528MHz + * MMDC channels: Both MMDC0, MMDC1 + *Density per CS in Gb: 256M + * Chip Selects used: 2 + * Number of Banks: 8 + * Row address: 14 + * Column address: 9 + * Data bus width 32 + */ + +/* MMDC_P0_BASE_ADDR = 0x021b0000 */ +/* MMDC_P1_BASE_ADDR = 0x021b4000 */ + +/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ +DATA 4 0x021b001c 0x00008000 + +/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */ +DATA 4 0x021b401c 0x00008000 + +/*LPDDR2 ZQ params */ +DATA 4 0x021b085c 0x1b5f01ff +DATA 4 0x021b485c 0x1b5f01ff + +/* Calibration setup. */ +/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */ +DATA 4 0x021b0800 0xa1390003 + +/*ca bus abs delay */ +DATA 4 0x021b0890 0x00400000 +/*ca bus abs delay */ +DATA 4 0x021b4890 0x00400000 +/* values of 20,40,50,60,7f tried. no difference seen */ + +/* DDR_PHY_P1_MPWRCADL */ +DATA 4 0x021b48bc 0x00055555 + +/*frc_msr.*/ +DATA 4 0x021b08b8 0x00000800 +/*frc_msr.*/ +DATA 4 0x021b48b8 0x00000800 + +/* DDR_PHY_P0_MPREDQBY0DL3 */ +DATA 4 0x021b081c 0x33333333 +/* DDR_PHY_P0_MPREDQBY1DL3 */ +DATA 4 0x021b0820 0x33333333 +/* DDR_PHY_P0_MPREDQBY2DL3 */ +DATA 4 0x021b0824 0x33333333 +/* DDR_PHY_P0_MPREDQBY3DL3 */ +DATA 4 0x021b0828 0x33333333 +/* DDR_PHY_P1_MPREDQBY0DL3 */ +DATA 4 0x021b481c 0x33333333 +/* DDR_PHY_P1_MPREDQBY1DL3 */ +DATA 4 0x021b4820 0x33333333 +/* DDR_PHY_P1_MPREDQBY2DL3 */ +DATA 4 0x021b4824 0x33333333 +/* DDR_PHY_P1_MPREDQBY3DL3 */ +DATA 4 0x021b4828 0x33333333 + +/* + * Read and write data delay, per byte. + * For optimized DDR operation it is recommended to run mmdc_calibration + * on your board, and replace 4 delay register assigns with resulted values + * Note: + * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section + * should be skipped, or the write/read calibration comming after that + * will stall + * b. The calibration code that runs for both MMDC0 & MMDC1 should be used. + */ + +DATA 4 0x021b0848 0x4b4b524f +DATA 4 0x021b4848 0x494f4c44 + +DATA 4 0x021b0850 0x3c3d303c +DATA 4 0x021b4850 0x3c343d38 + +/*dqs gating dis */ +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x0 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x0 + +/*clk delay */ +DATA 4 0x021b0858 0xa00 +/*clk delay */ +DATA 4 0x021b4858 0xa00 + +/*frc_msr */ +DATA 4 0x021b08b8 0x00000800 +/*frc_msr */ +DATA 4 0x021b48b8 0x00000800 +/* Calibration setup end */ + +/* Channel0 - startng address 0x80000000 */ +/* MMDC0_MDCFG0 */ +DATA 4 0x021b000c 0x34386145 + +/* MMDC0_MDPDC */ +DATA 4 0x021b0004 0x00020036 +/* MMDC0_MDCFG1 */ +DATA 4 0x021b0010 0x00100c83 +/* MMDC0_MDCFG2 */ +DATA 4 0x021b0014 0x000000Dc +/* MMDC0_MDMISC */ +DATA 4 0x021b0018 0x0000174C +/* MMDC0_MDRWD;*/ +DATA 4 0x021b002c 0x0f9f26d2 +/* MMDC0_MDOR */ +DATA 4 0x021b0030 0x0000020e +/* MMDC0_MDCFG3LP */ +DATA 4 0x021b0038 0x00190778 +/* MMDC0_MDOTC */ +DATA 4 0x021b0008 0x00000000 + +/* CS0_END */ +DATA 4 0x021b0040 0x0000005f +/* ROC */ +DATA 4 0x021b0404 0x0000000f + +/* MMDC0_MDCTL */ +DATA 4 0x021b0000 0xc3010000 + +/* Channel1 - starting address 0x10000000 */ +/* MMDC1_MDCFG0 */ +DATA 4 0x021b400c 0x34386145 + +/* MMDC1_MDPDC */ +DATA 4 0x021b4004 0x00020036 +/* MMDC1_MDCFG1 */ +DATA 4 0x021b4010 0x00100c83 +/* MMDC1_MDCFG2 */ +DATA 4 0x021b4014 0x000000Dc +/* MMDC1_MDMISC */ +DATA 4 0x021b4018 0x0000174C +/* MMDC1_MDRWD;*/ +DATA 4 0x021b402c 0x0f9f26d2 +/* MMDC1_MDOR */ +DATA 4 0x021b4030 0x0000020e +/* MMDC1_MDCFG3LP */ +DATA 4 0x021b4038 0x00190778 +/* MMDC1_MDOTC */ +DATA 4 0x021b4008 0x00000000 + +/* CS0_END */ +DATA 4 0x021b4040 0x0000003f + +/* MMDC1_MDCTL */ +DATA 4 0x021b4000 0xc3010000 + +/* Channel0 : Configure DDR device:*/ +/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ +DATA 4 0x021b001c 0x003f8030 +/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ +DATA 4 0x021b001c 0xff0a8030 +/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ +DATA 4 0x021b001c 0xa2018030 +/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ +DATA 4 0x021b001c 0x06028030 +/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ +DATA 4 0x021b001c 0x01038030 + +/* Channel1 : Configure DDR device:*/ +/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */ +DATA 4 0x021b401c 0x003f8030 +/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */ +DATA 4 0x021b401c 0xff0a8030 +/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */ +DATA 4 0x021b401c 0xa2018030 +/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */ +DATA 4 0x021b401c 0x06028030 +/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */ +DATA 4 0x021b401c 0x01038030 + +/* MMDC0_MDREF */ +DATA 4 0x021b0020 0x00005800 +/* MMDC1_MDREF */ +DATA 4 0x021b4020 0x00005800 + +/* DDR_PHY_P0_MPODTCTRL */ +DATA 4 0x021b0818 0x0 +/* DDR_PHY_P1_MPODTCTRL */ +DATA 4 0x021b4818 0x0 + +/* + * calibration values based on calibration compare of 0x00ffff00: + * Note, these calibration values are based on Freescale's board + * May need to run calibration on target board to fine tune these + */ + +/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */ +DATA 4 0x021b0800 0xa1310003 + +/* DDR_PHY_P0_MPMUR0, frc_msr */ +DATA 4 0x021b08b8 0x00000800 +/* DDR_PHY_P1_MPMUR0, frc_msr */ +DATA 4 0x021b48b8 0x00000800 + +/* + * MMDC0_MDSCR, clear this register + * (especially the configuration bit as initialization is complete) + */ +DATA 4 0x021b001c 0x00000000 +/* + * MMDC0_MDSCR, clear this register + * (especially the configuration bit as initialization is complete) + */ +DATA 4 0x021b401c 0x00000000 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +DATA 4 0x020e0010 0xF00000CF +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +#else /* CONFIG_MX6DL_LPDDR2 */ + +DATA 4 0x020e0798 0x000c0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e0590 0x00003000 +DATA 4 0x020e0598 0x00003000 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b4800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x00370037 +DATA 4 0x021b4810 0x00370037 +DATA 4 0x021b083c 0x422f0220 +DATA 4 0x021b0840 0x021f0219 +DATA 4 0x021b483C 0x422f0220 +DATA 4 0x021b4840 0x022d022f +DATA 4 0x021b0848 0x47494b49 +DATA 4 0x021b4848 0x48484c47 +DATA 4 0x021b0850 0x39382b2f +DATA 4 0x021b4850 0x2f35312c +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 + +DATA 4 0x021b000c 0x40445323 +DATA 4 0x021b0010 0xb66e8c63 + +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00081740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00440e21 +#ifdef CONFIG_DDR_32BIT +DATA 4 0x021b0040 0x00000017 +DATA 4 0x021b0000 0xc3190000 +#else +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0xc31a0000 +#endif +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x0400803a +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x0000803b +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00428039 +DATA 4 0x021b001c 0x07208030 +DATA 4 0x021b001c 0x07208038 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b001c 0x04008048 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00000007 +DATA 4 0x021b4818 0x00000007 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b4004 0x00011006 +DATA 4 0x021b001c 0x00000000 + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +DATA 4 0x020e0010 0xF00000CF +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif /* CONFIG_MX6DL_LPDDR2 */ diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 6c51f3a182..667dca532f 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -32,7 +32,12 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); +#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ + defined(CONFIG_DDR_32BIT) + gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2; +#else + gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; +#endif return 0; } @@ -224,7 +229,11 @@ int board_init(void) int checkboard(void) { +#ifdef CONFIG_MX6DL + puts("Board: MX6DL-Armadillo2\n"); +#else puts("Board: MX6Q-Armadillo2\n"); +#endif return 0; } diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 836d7221b0..1cb7561759 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -50,12 +50,12 @@ int dram_init(void) return 0; } -iomux_v3_cfg_t const uart4_pads[] = { +static iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; -iomux_v3_cfg_t const enet_pads[] = { +static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -74,7 +74,7 @@ iomux_v3_cfg_t const enet_pads[] = { }; /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ -struct i2c_pads_info i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, @@ -91,7 +91,7 @@ struct i2c_pads_info i2c_pad_info1 = { * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, * Compass Sensor, Accelerometer, Res Touch */ -struct i2c_pads_info i2c_pad_info2 = { +static struct i2c_pads_info i2c_pad_info2 = { .scl = { .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, @@ -104,11 +104,11 @@ struct i2c_pads_info i2c_pad_info2 = { } }; -iomux_v3_cfg_t const i2c3_pads[] = { +static iomux_v3_cfg_t const i2c3_pads[] = { MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -iomux_v3_cfg_t const port_exp[] = { +static iomux_v3_cfg_t const port_exp[] = { MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), }; @@ -117,7 +117,7 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); } -iomux_v3_cfg_t const usdhc3_pads[] = { +static iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -138,7 +138,7 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[1] = { {USDHC3_BASE_ADDR}, }; diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg index bb6c60b4c3..bb6c60b4c3 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 5eaec1bdb1..68d37184a3 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -157,7 +157,7 @@ int board_eth_init(bd_t *bis) #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC */ -struct i2c_pads_info i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, diff --git a/board/freescale/vf610twr/MAINTAINERS b/board/freescale/vf610twr/MAINTAINERS index 56a09c9ad9..f2997f05c3 100644 --- a/board/freescale/vf610twr/MAINTAINERS +++ b/board/freescale/vf610twr/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/vf610twr/ F: include/configs/vf610twr.h F: configs/vf610twr_defconfig +F: configs/vf610twr_nand_defconfig diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 54a9f2c7c3..b634965ad2 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -45,6 +45,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_A3__DDR_A_3, VF610_PAD_DDR_A2__DDR_A_2, VF610_PAD_DDR_A1__DDR_A_1, + VF610_PAD_DDR_A0__DDR_A_0, VF610_PAD_DDR_BA2__DDR_BA_2, VF610_PAD_DDR_BA1__DDR_BA_1, VF610_PAD_DDR_BA0__DDR_BA_0, @@ -76,6 +77,7 @@ void setup_iomux_ddr(void) VF610_PAD_DDR_WE__DDR_WE_B, VF610_PAD_DDR_ODT1__DDR_ODT_0, VF610_PAD_DDR_ODT0__DDR_ODT_1, + VF610_PAD_DDR_RESETB, }; imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); @@ -88,30 +90,30 @@ void ddr_phy_init(void) writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); - writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]); + + /* LPDDR2 only parameter */ + writel(DDRMC_PHY_OFF, &ddrmr->phy[49]); writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]); + + /* Processor Pad ODT settings */ + writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]); } void ddr_ctrl_init(void) @@ -120,12 +122,12 @@ void ddr_ctrl_init(void) writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]); - writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]); + writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]); - writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]); + writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]); writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]); - writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) | - DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]); + writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4), + &ddrmr->cr[13]); writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) | DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]); writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]); @@ -134,24 +136,23 @@ void ddr_ctrl_init(void) writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]); writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); - writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT | - DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); + writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); - writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]); + writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]); writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]); writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]); writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); - writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); - writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]); + writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]); + writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]); writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]); writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]); - writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]); + writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]); writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]); - writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]); + writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]); writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); @@ -164,37 +165,45 @@ void ddr_ctrl_init(void) writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]); - writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]); + writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]); writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) | DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]); writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | - DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255), + DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64), &ddrmr->cr[74]); writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | DDRMC_CR75_PLEN, &ddrmr->cr[75]); writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) | - DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]); + DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); - writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); - writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]); + writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12), + &ddrmr->cr[78]); + writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); - writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0, - &ddrmr->cr[87]); + writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]); writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]); + writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]); + writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]); + writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]); + + writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN, + &ddrmr->cr[102]); - writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]); - writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]); - writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]); + writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]); + writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]); + writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]); + writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]); + writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]); - writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), + writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]); writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]); @@ -205,23 +214,40 @@ void ddr_ctrl_init(void) &ddrmr->cr[121]); writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); - writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1), - &ddrmr->cr[123]); + writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]); writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]); - writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]); + writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]); writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]); + writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]); + writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1), + &ddrmr->cr[138]); writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]); + writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]); + writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128), + &ddrmr->cr[143]); + writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | + DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3), + &ddrmr->cr[144]); + writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]); + writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]); + writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]); + writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]); + writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]); writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1) | - DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]); - writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), + DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]); + writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); + writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | + DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]); ddr_phy_init(); @@ -278,6 +304,39 @@ static void setup_iomux_i2c(void) imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); } +#ifdef CONFIG_NAND_VF610_NFC +static void setup_iomux_nfc(void) +{ + static const iomux_v3_cfg_t nfc_pads[] = { + VF610_PAD_PTD31__NF_IO15, + VF610_PAD_PTD30__NF_IO14, + VF610_PAD_PTD29__NF_IO13, + VF610_PAD_PTD28__NF_IO12, + VF610_PAD_PTD27__NF_IO11, + VF610_PAD_PTD26__NF_IO10, + VF610_PAD_PTD25__NF_IO9, + VF610_PAD_PTD24__NF_IO8, + VF610_PAD_PTD23__NF_IO7, + VF610_PAD_PTD22__NF_IO6, + VF610_PAD_PTD21__NF_IO5, + VF610_PAD_PTD20__NF_IO4, + VF610_PAD_PTD19__NF_IO3, + VF610_PAD_PTD18__NF_IO2, + VF610_PAD_PTD17__NF_IO1, + VF610_PAD_PTD16__NF_IO0, + VF610_PAD_PTB24__NF_WE_B, + VF610_PAD_PTB25__NF_CE0_B, + VF610_PAD_PTB27__NF_RE_B, + VF610_PAD_PTC26__NF_RB_B, + VF610_PAD_PTC27__NF_ALE, + VF610_PAD_PTC28__NF_CLE + }; + + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); +} +#endif + + static void setup_iomux_qspi(void) { static const iomux_v3_cfg_t qspi0_pads[] = { @@ -354,6 +413,8 @@ static void clock_init(void) CCM_CCGR7_SDHC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, + CCM_CCGR10_NFC_CTRL_MASK); clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); @@ -373,14 +434,17 @@ static void clock_init(void) CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_ARM_CLK_DIV(0)); clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, - CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3)); + CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | + CCM_CSCMR1_NFC_CLK_SEL(0)); clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, CCM_CSCDR1_RMII_CLK_EN); clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, - CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0)); + CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | + CCM_CSCDR2_NFC_EN); clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | - CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3)); + CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | + CCM_CSCDR3_NFC_PRE_DIV(5)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(0)); } @@ -411,6 +475,9 @@ int board_early_init_f(void) setup_iomux_enet(); setup_iomux_i2c(); setup_iomux_qspi(); +#ifdef CONFIG_NAND_VF610_NFC + setup_iomux_nfc(); +#endif return 0; } |