armv8: ls2080ardb: Add LS2081ARDB board support

LS2081ARDB board is similar to LS2080ARDB board with few differences
 It hosts LS2081A SoC
 Default boot source is QSPI-boot
 It does not have IFC interface
 RTC and QSPI flash device are different
 It provides QIXIS access via I2C

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

4 files changed, 92 insertions, 3 deletions

diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index 2f0465fbba..8f64642593 100644
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -16,3 +16,21 @@ config SYS_CONFIG_NAME
 source "board/freescale/common/Kconfig"
 
 endif
+
+if TARGET_LS2081ARDB
+
+config SYS_BOARD
+	default "ls2080ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls2080ardb"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 3175ba3836..91f13ea717 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -12,6 +12,11 @@ M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	configs/ls2088ardb_qspi_defconfig
 
+LS2081ARDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2081ardb_defconfig
+
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <saksham.jain@nxp.freescale.com>
 S:	Maintained
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 873aadfab1..fde143d2f4 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -4,10 +4,14 @@ The LS2080A Reference Design (RDB) is a high-performance computing,
 evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
 Layerscape Architecture processor.
 
-LS2080A, LS2088A SoC Overview
---------------------
+The LS2081A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2081A
+Layerscape Architecture processor.More details in below sections
+
+LS2080A, LS2088A, LS2081A SoC Overview
+--------------------------------------
 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
-LS2088A SoC overview.
+LS2081A, LS2088A SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
@@ -38,6 +42,16 @@ LS2088A SoC overview.
  - UART
  - ARM JTAG support
 
+ LS2081ARDB board Overview
+ -------------------------
+ LS2081ARDB board is similar to LS2080ARDB board
+ with few differences like
+  - Hosts LS2081A SoC
+  - Default boot source is QSPI-boot
+  - Does not have IFC interface
+  - RTC and QSPI flash devices are different
+  - Provides QIXIS access via I2C
+
 Memory map from core's view
 ----------------------------
 0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 10e8ea4e42..df2d768718 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -68,6 +68,44 @@ int checkboard(void)
 	cpu_name(buf);
 	printf("Board: %s-RDB, ", buf);
 
+#ifdef CONFIG_TARGET_LS2081ARDB
+#ifdef CONFIG_FSL_QIXIS
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, ", (sw & 0xf) + 'A');
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
+	switch (sw) {
+	case 0:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 1:
+		puts("boot from QSPI DEV#1\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 2:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 3:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 4:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI EMU\n");
+		break;
+	default:
+		printf("invalid setting of SW%u\n", sw);
+		break;
+	}
+#endif
+	puts("SERDES1 Reference : ");
+	printf("Clock1 = 100MHz ");
+	printf("Clock2 = 161.13MHz");
+#else
 #ifdef CONFIG_FSL_QIXIS
 	sw = QIXIS_READ(arch);
 	printf("Board Arch: V%d, ", sw >> 4);
@@ -88,6 +126,7 @@ int checkboard(void)
 	puts("SERDES1 Reference : ");
 	printf("Clock1 = 156.25MHz ");
 	printf("Clock2 = 156.25MHz");
+#endif
 
 	puts("\nSERDES2 Reference : ");
 	printf("Clock1 = 100MHz ");
@@ -209,6 +248,9 @@ int board_init(void)
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
 	fsl_lsch3_early_init_f();
 	return 0;
 }
@@ -216,6 +258,11 @@ int board_early_init_f(void)
 int misc_init_r(void)
 {
 #ifdef CONFIG_FSL_QIXIS
+	/*
+	 * LS2081ARDB has smart voltage translator which needs
+	 * to be programmed as below
+	 */
+#ifndef CONFIG_TARGET_LS2081ARDB
 	u8 sw;
 
 	sw = QIXIS_READ(arch);
@@ -225,12 +272,15 @@ int misc_init_r(void)
 	 * by setting GPIO4_10 output to zero
 	 */
 	if ((sw & 0xf) == 0x5) {
+#endif
 		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
 					    in_le32(GPIO4_GPDIR_ADDR)));
 		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
 					    in_le32(GPIO4_GPDAT_ADDR)));
+#ifndef CONFIG_TARGET_LS2081ARDB
 	}
 #endif
+#endif
 
 	if (hwconfig("sdhc"))
 		config_board_mux(MUX_TYPE_SDHC);
@@ -350,6 +400,7 @@ void update_spd_address(unsigned int ctrl_num,
 			unsigned int slot,
 			unsigned int *addr)
 {
+#ifndef CONFIG_TARGET_LS2081ARDB
 #ifdef CONFIG_FSL_QIXIS
 	u8 sw;
 
@@ -361,4 +412,5 @@ void update_spd_address(unsigned int ctrl_num,
 			*addr = SPD_EEPROM_ADDRESS3;
 	}
 #endif
+#endif
 }