MLK-23574-47 imx8mq: Add DDR3L and DDR4 validation boards

Porting board codes, configurations, DTS and DDR initialization codes
for the DDR3L and DDR4 validation boards from imx_v2019.04

Supported modules
   - DDR3L VAL: Two RANK DDR3L, QSPI B, eMMC/SD, RMII ENET, UART.
   - DDR4  VAL: Two RANK DDR4, SD, NAND, RGMII ENET, UART

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit ff5d678353f0f442902a2a3067fad198c7a7dacc)
(cherry picked from commit b779c24473711a75b7455e99662ca7a69eb9c6bc)
(cherry picked from commit 63ed4473ba855540cdac7faa13c7126b10aabeb0)

11 files changed, 2905 insertions, 0 deletions

diff --git a/board/freescale/imx8mq_val/Kconfig b/board/freescale/imx8mq_val/Kconfig
new file mode 100644
index 00000000000..0b74a66fe99
--- /dev/null
+++ b/board/freescale/imx8mq_val/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MQ_DDR3L_VAL || TARGET_IMX8MQ_DDR4_VAL
+
+config SYS_BOARD
+	default "imx8mq_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_val"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
diff --git a/board/freescale/imx8mq_val/Makefile b/board/freescale/imx8mq_val/Makefile
new file mode 100644
index 00000000000..f39274ab05f
--- /dev/null
+++ b/board/freescale/imx8mq_val/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_val.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr/helper.o
+ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+obj-y += ddr/ddr3l/ddr_init.o ddr/ddr3l/ddrphy_train.o
+else
+obj-y += ddr/ddr4/ddr_init.o ddr/ddr4/ddrphy_train.o
+endif
+endif
diff --git a/board/freescale/imx8mq_val/ddr/ddr.h b/board/freescale/imx8mq_val/ddr/ddr.h
new file mode 100644
index 00000000000..b42b04c1ebe
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/ddr.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef SRC_DDRC_RCR_ADDR
+#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
+#endif
+#ifndef DDR_CSD1_BASE_ADDR
+#define DDR_CSD1_BASE_ADDR 0x40000000
+#endif
+
+void ddr_load_train_code(enum fw_type type);
+int wait_ddrphy_training_complete(void);
+void ddr3_phyinit_train_1600mts(void);
+void ddr4_phyinit_train_2400mts(void);
diff --git a/board/freescale/imx8mq_val/ddr/ddr3l/ddr_init.c b/board/freescale/imx8mq_val/ddr/ddr3l/ddr_init.c
new file mode 100644
index 00000000000..0dfbb4a4a00
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/ddr3l/ddr_init.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include "../ddr.h"
+
+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
+#define ddr_printf(args...) printf(args)
+#else
+#define ddr_printf(args...)
+#endif
+
+#include "../wait_ddrphy_training_complete.c"
+
+static inline void reg32clrbit(unsigned long addr, u32 bit)
+{
+	clrbits_le32(addr, (1 << bit));
+}
+
+volatile unsigned int tmp;
+void umctl2_cfg(void){
+	reg32_write(DDRC_DBG1(0), 0x00000001);
+	reg32_write(DDRC_PWRCTL(0), 0x00000001);
+	do{
+	  tmp = 0x7 & (reg32_read(DDRC_STAT(0)));
+	} while (tmp);/* wait init state */
+
+	reg32_write(DDRC_MSTR(0), 0x83040001);/* two rank */
+
+	reg32_write(DDRC_MRCTRL0(0), 0x40004030);
+	reg32_write(DDRC_MRCTRL1(0), 0x0001c68e);
+	reg32_write(DDRC_MRCTRL2(0), 0x921b7e95);
+	reg32_write(DDRC_DERATEEN(0), 0x00000506);
+	reg32_write(DDRC_DERATEINT(0), 0x9a4fbdf1);
+	reg32_write(DDRC_MSTR2(0), 0x00000001);
+	reg32_write(DDRC_PWRCTL(0), 0x000000a8);
+	reg32_write(DDRC_PWRTMG(0), 0x00532203);
+	reg32_write(DDRC_HWLPCTL(0), 0x0b6d0000);
+	reg32_write(DDRC_HWFFCCTL(0), 0x00000030);
+	reg32_write(DDRC_RFSHCTL0(0), 0x00203020);
+	reg32_write(DDRC_RFSHCTL1(0), 0x0001000d);
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+	reg32_write(DDRC_RFSHTMG(0), 0x0061008c);
+	reg32_write(DDRC_CRCPARCTL0(0), 0x00000000);
+	reg32_write(DDRC_CRCPARCTL1(0), 0x00000000);
+	reg32_write(DDRC_INIT0(0), 0xc0030002);
+	reg32_write(DDRC_INIT1(0), 0x0001000b);
+	reg32_write(DDRC_INIT2(0), 0x00006303);
+	reg32_write(DDRC_INIT3(0), 0x0d700044);/* MR1, MR0 */
+	reg32_write(DDRC_INIT4(0), 0x00180000);/* MR2 */
+	reg32_write(DDRC_INIT5(0), 0x00090071);
+	reg32_write(DDRC_INIT6(0), 0x00000000);
+	reg32_write(DDRC_INIT7(0), 0x00000000);
+	reg32_write(DDRC_DIMMCTL(0), 0x00000032);
+	reg32_write(DDRC_RANKCTL(0), 0x00000ee5);
+	reg32_write(DDRC_DRAMTMG0(0), 0x0c101a0e);
+	reg32_write(DDRC_DRAMTMG1(0), 0x000a0314);
+	reg32_write(DDRC_DRAMTMG2(0), 0x04060509);
+	reg32_write(DDRC_DRAMTMG3(0), 0x00002006);
+	reg32_write(DDRC_DRAMTMG4(0), 0x06020306);
+	reg32_write(DDRC_DRAMTMG5(0), 0x0b060202);
+	reg32_write(DDRC_DRAMTMG6(0), 0x060a0009);
+	reg32_write(DDRC_DRAMTMG7(0), 0x0000060b);
+	reg32_write(DDRC_DRAMTMG8(0), 0x01017c0a);
+	reg32_write(DDRC_DRAMTMG9(0), 0x4000000e);
+	reg32_write(DDRC_DRAMTMG10(0), 0x00070803);
+	reg32_write(DDRC_DRAMTMG11(0), 0x0101000b);
+	reg32_write(DDRC_DRAMTMG12(0), 0x00000000);
+	reg32_write(DDRC_DRAMTMG13(0), 0x5d000000);
+	reg32_write(DDRC_DRAMTMG14(0), 0x00000b39);
+	reg32_write(DDRC_DRAMTMG15(0), 0x80000000);
+	reg32_write(DDRC_DRAMTMG17(0), 0x00f1006a);
+	reg32_write(DDRC_ZQCTL0(0), 0x50800020);
+	reg32_write(DDRC_ZQCTL1(0), 0x00000070);
+	reg32_write(DDRC_ZQCTL2(0), 0x00000000);
+	reg32_write(DDRC_DFITMG0(0), 0x03868203);
+	reg32_write(DDRC_DFITMG1(0), 0x00020103);
+	reg32_write(DDRC_DFILPCFG0(0), 0x07713121);
+	reg32_write(DDRC_DFILPCFG1(0), 0x00000010);
+	reg32_write(DDRC_DFIUPD0(0), 0xe0400018);
+	reg32_write(DDRC_DFIUPD1(0), 0x0005003c);
+	reg32_write(DDRC_DFIUPD2(0), 0x00000000);
+	reg32_write(DDRC_DFIMISC(0), 0x00000011);
+	reg32_write(DDRC_DFITMG2(0), 0x00000603);
+	reg32_write(DDRC_DFITMG3(0), 0x00000001);
+	reg32_write(DDRC_DBICTL(0), 0x00000001);
+	reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000);
+
+	reg32_write(DDRC_ADDRMAP0(0), 0x00000016); /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */
+	reg32_write(DDRC_ADDRMAP1(0), 0x00080808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */
+	reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2;  [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */
+	reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6;  [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */
+	reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */
+	reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6;  [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */
+	reg32_write(DDRC_ADDRMAP6(0), 0x0f070707); /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */
+	reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f);
+	reg32_write(DDRC_ADDRMAP8(0), 0x00000000); /* [5:0] bg-b0; [13:8]bg-b1 */
+	reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	reg32_write(DDRC_ADDRMAP11(0), 0x00000000);
+
+
+	reg32_write(DDRC_ODTCFG(0), 0x041d0f5c);
+	reg32_write(DDRC_ODTMAP(0), 0x00000201);
+	reg32_write(DDRC_SCHED(0), 0x7ab50b07);
+	reg32_write(DDRC_SCHED1(0), 0x00000022);
+	reg32_write(DDRC_PERFHPR1(0), 0x7b00665e);
+	reg32_write(DDRC_PERFLPR1(0), 0x2b00c4e1);
+	reg32_write(DDRC_PERFWR1(0), 0xb700c9fe);
+	reg32_write(DDRC_DBG0(0), 0x00000017);
+	reg32_write(DDRC_DBG1(0), 0x00000000);
+	reg32_write(DDRC_DBGCMD(0), 0x00000000);
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+	reg32_write(DDRC_POISONCFG(0), 0x00010000);
+	reg32_write(DDRC_PCCFG(0), 0x00000100);
+	reg32_write(DDRC_PCFGR_0(0), 0x00003051);
+	reg32_write(DDRC_PCFGW_0(0), 0x000061d2);
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+	reg32_write(DDRC_PCFGQOS0_0(0), 0x02100b04);
+	reg32_write(DDRC_PCFGQOS1_0(0), 0x003f0353);
+	reg32_write(DDRC_PCFGWQOS0_0(0), 0x00000002);
+	reg32_write(DDRC_PCFGWQOS1_0(0), 0x000005fd);
+}
+
+int ddr_init(struct dram_timing_info *timing_info)
+{
+	/* change the clock source of dram_apb_clk_root  */
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+		     CLK_ROOT_SOURCE_SEL(4) |
+		     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
+
+	/* disable the clock gating */
+	reg32_write(0x303A00EC,0x0000ffff);
+	reg32setbit(0x303A00F8,5);
+	reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
+
+	dram_pll_init(MHZ(400));
+
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+
+	/* Configure uMCTL2's registers */
+	umctl2_cfg();
+
+	reg32setbit(DDRC_RFSHCTL3(0),0); /* dis_auto_refresh */
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+
+	ddr_load_train_code(FW_1D_IMAGE);
+
+	reg32_write(DDRC_DBG1(0), 0x00000000); /* ('b00000000_00000000_00000000_00000000) ('d0) */
+	reg32setbit(DDRC_PWRCTL(0),5); /* selfref_sw=1, self-refresh */
+	reg32clrbit(DDRC_SWCTL(0), 0); /* sw_done=0, enable quasi-dynamic programming */
+	reg32_write(DDRC_DFIMISC(0), 0x00000000);
+
+	/* Configure DDR3L PHY's registers */
+	ddr3_phyinit_train_1600mts();
+
+	do {
+		tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097);
+	} while (tmp != 0);
+
+	reg32setbit(DDRC_DFIMISC(0),5);/* dfi_init_start=1 */
+	do{
+		tmp = 0x1 & (reg32_read(DDRC_DFISTAT(0)));
+	} while (!tmp);/*  wait DFISTAT.dfi_init_complete to 1 */
+
+	reg32clrbit(DDRC_DFIMISC(0),5);/* dfi_init_start=0 */
+	reg32setbit(DDRC_DFIMISC(0),0);/* dfi_init_complete_en=1 */
+
+	reg32clrbit(DDRC_PWRCTL(0),5);/* selfref_sw=0, exit self-refresh */
+
+	reg32setbit(DDRC_SWCTL(0), 0);/* sw_done=1, disable quasi-dynamic programming */
+
+	/* wait SWSTAT.sw_done_ack to 1 */
+	do{
+		tmp = 0x1 & (reg32_read(DDRC_SWSTAT(0)));
+	} while (!tmp);
+
+	/* wait STAT to normal state */
+	do{
+		tmp = 0x7 & (reg32_read(DDRC_STAT(0)));
+	} while (tmp != 0x1);
+
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001); /* enable port 0 */
+
+	reg32clrbit(DDRC_RFSHCTL3(0), 0); /* auto-refresh enable */
+
+	return 0;
+}
diff --git a/board/freescale/imx8mq_val/ddr/ddr3l/ddrphy_train.c b/board/freescale/imx8mq_val/ddr/ddr3l/ddrphy_train.c
new file mode 100644
index 00000000000..066ca7ff4b5
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/ddr3l/ddrphy_train.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include "../ddr.h"
+
+#define DDR3_MR1_RTT120_RON40   ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=00:40ohm */
+#define DDR3_MR1_RTT120_RON34   ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=01:34ohm */
+#define DDR3_MR1_RTT60_RON40    ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=00:40ohm */
+#define DDR3_MR1_RTT60_RON34    ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=01:34ohm */
+#define DDR3_MR1_RTT40_RON34    ((0L << 9) | (1L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=011:40ohm;Ron:M[5,1]=01:34ohm */
+#define DDR3_MR1_RTT_DIS_RON40  ((0L << 9) | (0L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=000:disable;Ron:M[5,1]=00:40ohm */
+
+#define DDR3_PHY_RON40    40 /* 40ohm */
+#define DDR3_PHY_RON34    34 /* 34ohm */
+
+#define DDR3_PHY_RTT120   120 /* 120ohm */
+#define DDR3_PHY_RTT60    60 /* 60ohm */
+#define DDR3_PHY_RTT40    40 /* 40ohm */
+#define DDR3_PHY_RTT48    48 /* 48ohm */
+
+#define DDR3_RTT_WR_DIS   0UL
+#define DDR3_RTT_WR_60    1UL
+#define DDR3_RTT_WR_120   2UL
+
+#define DDR3_MR1_VAL            DDR3_MR1_RTT120_RON40
+#define DDR3_MR2_RTT_WR_VAL     DDR3_RTT_WR_DIS
+
+#define DDR3_PHY_RON            DDR3_PHY_RON40
+#define DDR3_PHY_RTT            DDR3_PHY_RTT120
+
+
+void ddr3_phyinit_train_1600mts(void){
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0x1005f,0x3ff); /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1015f,0x3ff); /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1105f,0x3ff); /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1115f,0x3ff); /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1205f,0x3ff); /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1215f,0x3ff); /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1305f,0x3ff); /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1315f,0x3ff); /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */
+
+	dwc_ddrphy_apb_wr(0x55,0x3ff); /*  DWC_DDRPHYA_ANIB0_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x1055,0x3ff); /*  DWC_DDRPHYA_ANIB1_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x2055,0x3ff); /*  DWC_DDRPHYA_ANIB2_ATxSlewRat */
+	dwc_ddrphy_apb_wr(0x3055,0x3ff); /*  DWC_DDRPHYA_ANIB3_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x4055,0xff); /*  DWC_DDRPHYA_ANIB4_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x5055,0xff); /*  DWC_DDRPHYA_ANIB5_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x6055,0x3ff); /*  DWC_DDRPHYA_ANIB6_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x7055,0x3ff); /*  DWC_DDRPHYA_ANIB7_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x8055,0x3ff); /*  DWC_DDRPHYA_ANIB8_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x9055,0x3ff); /*  DWC_DDRPHYA_ANIB9_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x200c5,0xb); /*  DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */
+	dwc_ddrphy_apb_wr(0x2002e,0x1); /*  DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */
+
+	dwc_ddrphy_apb_wr(0x20024,0x8); /*  DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */
+	dwc_ddrphy_apb_wr(0x2003a,0x0); /*  DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
+	dwc_ddrphy_apb_wr(0x20056,0xa); /*  DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */
+	dwc_ddrphy_apb_wr(0x1004d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1014d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1104d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1114d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1204d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1214d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1304d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1314d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x10049,0xe38); /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x10149,0xe38); /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x11049,0xe38); /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x11149,0xe38); /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x12049,0xe38); /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x12149,0xe38); /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x13049,0xe38); /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x13149,0xe38); /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x43,0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x1043,0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x2043,0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x3043,0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x4043,0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x5043,0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x6043,0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x7043,0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x8043,0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x9043,0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x20018,0x5); /*  DWC_DDRPHYA_MASTER0_DfiMode */
+	dwc_ddrphy_apb_wr(0x20075,0x0); /*  DWC_DDRPHYA_MASTER0_DfiCAMode */
+	dwc_ddrphy_apb_wr(0x20050,0x0); /*  DWC_DDRPHYA_MASTER0_CalDrvStr0 */
+	dwc_ddrphy_apb_wr(0x20008,0x190); /*  DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */
+	dwc_ddrphy_apb_wr(0x20088,0x9); /*  DWC_DDRPHYA_MASTER0_CalRate */
+	dwc_ddrphy_apb_wr(0x200b2,0xf8); /*  DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */
+	dwc_ddrphy_apb_wr(0x10043,0x581); /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x10143,0x581); /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x11043,0x581); /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x11143,0x581); /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x12043,0x581); /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x12143,0x581); /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x13043,0x581); /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x13143,0x581); /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x200fa,0x1); /*  DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */
+	dwc_ddrphy_apb_wr(0x20019,0x5); /*  DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */
+	dwc_ddrphy_apb_wr(0x200f0,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
+	dwc_ddrphy_apb_wr(0x200f1,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */
+	dwc_ddrphy_apb_wr(0x200f2,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */
+	dwc_ddrphy_apb_wr(0x200f3,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */
+	dwc_ddrphy_apb_wr(0x200f4,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */
+	dwc_ddrphy_apb_wr(0x200f5,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */
+	dwc_ddrphy_apb_wr(0x200f6,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */
+	dwc_ddrphy_apb_wr(0x200f7,0xf000); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */
+	dwc_ddrphy_apb_wr(0x2000b,0x33); /*  DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
+	dwc_ddrphy_apb_wr(0x2000c,0x65); /*  DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
+	dwc_ddrphy_apb_wr(0x2000d,0x3e9); /*  DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
+	dwc_ddrphy_apb_wr(0x2000e,0x2c); /*  DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
+	dwc_ddrphy_apb_wr(0x20025,0x0); /*  DWC_DDRPHYA_MASTER0_MasterX4Config */
+	dwc_ddrphy_apb_wr(0x2002d,0x0); /*  DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */
+
+	dwc_ddrphy_apb_wr(0x20060,0x2); /*  DWC_DDRPHYA_MASTER0_MemResetL */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0x54000,0x0);
+	dwc_ddrphy_apb_wr(0x54001,0x0);
+	dwc_ddrphy_apb_wr(0x54002,0x0);
+	dwc_ddrphy_apb_wr(0x54003,0x640);
+	dwc_ddrphy_apb_wr(0x54004,0x2);
+	dwc_ddrphy_apb_wr(0x54005,((DDR3_PHY_RON << 8) | (DDR3_PHY_RTT << 0)));
+	dwc_ddrphy_apb_wr(0x54006,0x13b);
+	dwc_ddrphy_apb_wr(0x54007,0x2000);
+
+	dwc_ddrphy_apb_wr(0x54008,0x303); /* two ranks */
+
+	dwc_ddrphy_apb_wr(0x54009,0x200);
+	dwc_ddrphy_apb_wr(0x5400a,0x0);
+	dwc_ddrphy_apb_wr(0x5400b,0x31f);
+	dwc_ddrphy_apb_wr(0x5400c,0xc8);
+
+	dwc_ddrphy_apb_wr(0x54012,0x1);
+	dwc_ddrphy_apb_wr(0x5402f,0xd70); /* MR0 */
+	dwc_ddrphy_apb_wr(0x54030,DDR3_MR1_VAL); /* MR1=6:Ron=34ohm/Rtt(NOM)=60ohm */
+	dwc_ddrphy_apb_wr(0x54031,(0x18 | (DDR3_MR2_RTT_WR_VAL << 9))); /*MR2 */
+	dwc_ddrphy_apb_wr(0x5403a,0x1221);
+	dwc_ddrphy_apb_wr(0x5403b,0x4884);
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0099,0x9); /*  DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0099,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0099,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroReset */
+
+	wait_ddrphy_training_complete();
+
+	dwc_ddrphy_apb_wr(0xd0099,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0x90000,0x10); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
+	dwc_ddrphy_apb_wr(0x90001,0x400); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
+	dwc_ddrphy_apb_wr(0x90002,0x10e); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
+	dwc_ddrphy_apb_wr(0x90003,0x0); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
+	dwc_ddrphy_apb_wr(0x90004,0x0); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
+	dwc_ddrphy_apb_wr(0x90005,0x8); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
+	dwc_ddrphy_apb_wr(0x90029,0xb); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
+	dwc_ddrphy_apb_wr(0x9002a,0x480); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
+	dwc_ddrphy_apb_wr(0x9002b,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
+	dwc_ddrphy_apb_wr(0x9002c,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
+	dwc_ddrphy_apb_wr(0x9002d,0x448); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
+	dwc_ddrphy_apb_wr(0x9002e,0x139); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
+	dwc_ddrphy_apb_wr(0x9002f,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
+	dwc_ddrphy_apb_wr(0x90030,0x478); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
+	dwc_ddrphy_apb_wr(0x90031,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
+	dwc_ddrphy_apb_wr(0x90032,0x2); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
+	dwc_ddrphy_apb_wr(0x90033,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
+	dwc_ddrphy_apb_wr(0x90034,0x139); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
+	dwc_ddrphy_apb_wr(0x90035,0xf); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
+	dwc_ddrphy_apb_wr(0x90036,0x7c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
+	dwc_ddrphy_apb_wr(0x90037,0x139); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
+	dwc_ddrphy_apb_wr(0x90038,0x44); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
+	dwc_ddrphy_apb_wr(0x90039,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
+	dwc_ddrphy_apb_wr(0x9003a,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
+	dwc_ddrphy_apb_wr(0x9003b,0x14f); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
+	dwc_ddrphy_apb_wr(0x9003c,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
+	dwc_ddrphy_apb_wr(0x9003d,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
+	dwc_ddrphy_apb_wr(0x9003e,0x47); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
+	dwc_ddrphy_apb_wr(0x9003f,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
+	dwc_ddrphy_apb_wr(0x90040,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
+	dwc_ddrphy_apb_wr(0x90041,0x4f); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
+	dwc_ddrphy_apb_wr(0x90042,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
+	dwc_ddrphy_apb_wr(0x90043,0x179); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
+	dwc_ddrphy_apb_wr(0x90044,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
+	dwc_ddrphy_apb_wr(0x90045,0xe0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
+	dwc_ddrphy_apb_wr(0x90046,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
+	dwc_ddrphy_apb_wr(0x90047,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
+	dwc_ddrphy_apb_wr(0x90048,0x7c8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
+	dwc_ddrphy_apb_wr(0x90049,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
+	dwc_ddrphy_apb_wr(0x9004a,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
+	dwc_ddrphy_apb_wr(0x9004b,0x1); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
+	dwc_ddrphy_apb_wr(0x9004c,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
+	dwc_ddrphy_apb_wr(0x9004d,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
+	dwc_ddrphy_apb_wr(0x9004e,0x45a); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
+	dwc_ddrphy_apb_wr(0x9004f,0x9); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
+	dwc_ddrphy_apb_wr(0x90050,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
+	dwc_ddrphy_apb_wr(0x90051,0x448); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
+	dwc_ddrphy_apb_wr(0x90052,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
+	dwc_ddrphy_apb_wr(0x90053,0x40); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
+	dwc_ddrphy_apb_wr(0x90054,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
+	dwc_ddrphy_apb_wr(0x90055,0x179); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
+	dwc_ddrphy_apb_wr(0x90056,0x1); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
+	dwc_ddrphy_apb_wr(0x90057,0x618); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
+	dwc_ddrphy_apb_wr(0x90058,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
+	dwc_ddrphy_apb_wr(0x90059,0x40c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
+	dwc_ddrphy_apb_wr(0x9005a,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
+	dwc_ddrphy_apb_wr(0x9005b,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
+	dwc_ddrphy_apb_wr(0x9005c,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
+	dwc_ddrphy_apb_wr(0x9005d,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
+	dwc_ddrphy_apb_wr(0x9005e,0x48); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
+	dwc_ddrphy_apb_wr(0x9005f,0x4040); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
+	dwc_ddrphy_apb_wr(0x90060,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
+	dwc_ddrphy_apb_wr(0x90061,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
+	dwc_ddrphy_apb_wr(0x90062,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
+	dwc_ddrphy_apb_wr(0x90063,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
+	dwc_ddrphy_apb_wr(0x90064,0x48); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
+	dwc_ddrphy_apb_wr(0x90065,0x40); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
+	dwc_ddrphy_apb_wr(0x90066,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
+	dwc_ddrphy_apb_wr(0x90067,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
+	dwc_ddrphy_apb_wr(0x90068,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
+	dwc_ddrphy_apb_wr(0x90069,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
+	dwc_ddrphy_apb_wr(0x9006a,0x18); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
+	dwc_ddrphy_apb_wr(0x9006b,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
+	dwc_ddrphy_apb_wr(0x9006c,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
+	dwc_ddrphy_apb_wr(0x9006d,0x78); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
+	dwc_ddrphy_apb_wr(0x9006e,0x549); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
+	dwc_ddrphy_apb_wr(0x9006f,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
+	dwc_ddrphy_apb_wr(0x90070,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
+	dwc_ddrphy_apb_wr(0x90071,0xd49); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
+	dwc_ddrphy_apb_wr(0x90072,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
+	dwc_ddrphy_apb_wr(0x90073,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
+	dwc_ddrphy_apb_wr(0x90074,0x94a); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
+	dwc_ddrphy_apb_wr(0x90075,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
+	dwc_ddrphy_apb_wr(0x90076,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
+	dwc_ddrphy_apb_wr(0x90077,0x441); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
+	dwc_ddrphy_apb_wr(0x90078,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
+	dwc_ddrphy_apb_wr(0x90079,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
+	dwc_ddrphy_apb_wr(0x9007a,0x42); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
+	dwc_ddrphy_apb_wr(0x9007b,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
+	dwc_ddrphy_apb_wr(0x9007c,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
+	dwc_ddrphy_apb_wr(0x9007d,0x1); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
+	dwc_ddrphy_apb_wr(0x9007e,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
+	dwc_ddrphy_apb_wr(0x9007f,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
+	dwc_ddrphy_apb_wr(0x90080,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
+	dwc_ddrphy_apb_wr(0x90081,0xe0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
+	dwc_ddrphy_apb_wr(0x90082,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
+	dwc_ddrphy_apb_wr(0x90083,0xa); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
+	dwc_ddrphy_apb_wr(0x90084,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
+	dwc_ddrphy_apb_wr(0x90085,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
+	dwc_ddrphy_apb_wr(0x90086,0x9); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
+	dwc_ddrphy_apb_wr(0x90087,0x3c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
+	dwc_ddrphy_apb_wr(0x90088,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
+	dwc_ddrphy_apb_wr(0x90089,0x9); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
+	dwc_ddrphy_apb_wr(0x9008a,0x3c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
+	dwc_ddrphy_apb_wr(0x9008b,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
+	dwc_ddrphy_apb_wr(0x9008c,0x18); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
+	dwc_ddrphy_apb_wr(0x9008d,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
+	dwc_ddrphy_apb_wr(0x9008e,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
+	dwc_ddrphy_apb_wr(0x9008f,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
+	dwc_ddrphy_apb_wr(0x90090,0x3c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
+	dwc_ddrphy_apb_wr(0x90091,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
+	dwc_ddrphy_apb_wr(0x90092,0x18); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
+	dwc_ddrphy_apb_wr(0x90093,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
+	dwc_ddrphy_apb_wr(0x90094,0x48); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
+	dwc_ddrphy_apb_wr(0x90095,0x18); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
+	dwc_ddrphy_apb_wr(0x90096,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
+	dwc_ddrphy_apb_wr(0x90097,0x58); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
+	dwc_ddrphy_apb_wr(0x90098,0xa); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
+	dwc_ddrphy_apb_wr(0x90099,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
+	dwc_ddrphy_apb_wr(0x9009a,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
+	dwc_ddrphy_apb_wr(0x9009b,0x2); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
+	dwc_ddrphy_apb_wr(0x9009c,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
+	dwc_ddrphy_apb_wr(0x9009d,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
+	dwc_ddrphy_apb_wr(0x9009e,0x7); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
+	dwc_ddrphy_apb_wr(0x9009f,0x7c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
+	dwc_ddrphy_apb_wr(0x900a0,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
+	dwc_ddrphy_apb_wr(0x900a1,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
+	dwc_ddrphy_apb_wr(0x900a2,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
+	dwc_ddrphy_apb_wr(0x900a3,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
+	dwc_ddrphy_apb_wr(0x900a4,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
+	dwc_ddrphy_apb_wr(0x900a5,0x8140); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
+	dwc_ddrphy_apb_wr(0x900a6,0x10c); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
+	dwc_ddrphy_apb_wr(0x900a7,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
+	dwc_ddrphy_apb_wr(0x900a8,0x8138); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
+	dwc_ddrphy_apb_wr(0x900a9,0x10c); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
+	dwc_ddrphy_apb_wr(0x900aa,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
+	dwc_ddrphy_apb_wr(0x900ab,0x7c8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
+	dwc_ddrphy_apb_wr(0x900ac,0x101); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
+	dwc_ddrphy_apb_wr(0x900ad,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
+	dwc_ddrphy_apb_wr(0x900ae,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
+	dwc_ddrphy_apb_wr(0x900af,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
+	dwc_ddrphy_apb_wr(0x900b0,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
+	dwc_ddrphy_apb_wr(0x900b1,0x448); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
+	dwc_ddrphy_apb_wr(0x900b2,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
+	dwc_ddrphy_apb_wr(0x900b3,0xf); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
+	dwc_ddrphy_apb_wr(0x900b4,0x7c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
+	dwc_ddrphy_apb_wr(0x900b5,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
+	dwc_ddrphy_apb_wr(0x900b6,0x47); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
+	dwc_ddrphy_apb_wr(0x900b7,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
+	dwc_ddrphy_apb_wr(0x900b8,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
+	dwc_ddrphy_apb_wr(0x900b9,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
+	dwc_ddrphy_apb_wr(0x900ba,0x618); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
+	dwc_ddrphy_apb_wr(0x900bb,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
+	dwc_ddrphy_apb_wr(0x900bc,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
+	dwc_ddrphy_apb_wr(0x900bd,0xe0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
+	dwc_ddrphy_apb_wr(0x900be,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
+	dwc_ddrphy_apb_wr(0x900bf,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
+	dwc_ddrphy_apb_wr(0x900c0,0x7c8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
+	dwc_ddrphy_apb_wr(0x900c1,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
+	dwc_ddrphy_apb_wr(0x900c2,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
+	dwc_ddrphy_apb_wr(0x900c3,0x8140); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
+	dwc_ddrphy_apb_wr(0x900c4,0x10c); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
+	dwc_ddrphy_apb_wr(0x900c5,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
+	dwc_ddrphy_apb_wr(0x900c6,0x1); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
+	dwc_ddrphy_apb_wr(0x900c7,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
+	dwc_ddrphy_apb_wr(0x900c8,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
+	dwc_ddrphy_apb_wr(0x900c9,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
+	dwc_ddrphy_apb_wr(0x900ca,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
+	dwc_ddrphy_apb_wr(0x900cb,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
+	dwc_ddrphy_apb_wr(0x900cc,0x7c8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
+	dwc_ddrphy_apb_wr(0x900cd,0x101); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
+	dwc_ddrphy_apb_wr(0x90006,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
+	dwc_ddrphy_apb_wr(0x90007,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
+	dwc_ddrphy_apb_wr(0x90008,0x8); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
+	dwc_ddrphy_apb_wr(0x90009,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
+	dwc_ddrphy_apb_wr(0x9000a,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
+	dwc_ddrphy_apb_wr(0x9000b,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
+	dwc_ddrphy_apb_wr(0xd00e7,0x400); /*  DWC_DDRPHYA_APBONLY0_SequencerOverride */
+	dwc_ddrphy_apb_wr(0x90017,0x0); /*  DWC_DDRPHYA_INITENG0_StartVector0b0 */
+	dwc_ddrphy_apb_wr(0x90026,0x2c); /*  DWC_DDRPHYA_INITENG0_StartVector0b15 */
+	dwc_ddrphy_apb_wr(0x9000c,0x0); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
+	dwc_ddrphy_apb_wr(0x9000d,0x173); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
+	dwc_ddrphy_apb_wr(0x9000e,0x60); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
+	dwc_ddrphy_apb_wr(0x9000f,0x6110); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
+	dwc_ddrphy_apb_wr(0x90010,0x2152); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
+	dwc_ddrphy_apb_wr(0x90011,0xdfbd); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
+	dwc_ddrphy_apb_wr(0x90012,0xffff); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
+	dwc_ddrphy_apb_wr(0x90013,0x6152); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
+	dwc_ddrphy_apb_wr(0xc0080,0x0); /*  DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+}
diff --git a/board/freescale/imx8mq_val/ddr/ddr4/ddr_init.c b/board/freescale/imx8mq_val/ddr/ddr4/ddr_init.c
new file mode 100644
index 00000000000..2f68c4c0ed2
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/ddr4/ddr_init.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include "../ddr.h"
+
+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
+#define ddr_printf(args...) printf(args)
+#else
+#define ddr_printf(args...)
+#endif
+
+#include "../wait_ddrphy_training_complete.c"
+
+volatile unsigned int tmp, tmp_t;
+void umctl2_cfg(void){
+	reg32_write(DDRC_DBG1(0), 0x00000001);
+	reg32_write(DDRC_PWRCTL(0), 0x00000001);
+	tmp = reg32_read(DDRC_STAT(0));
+	while (tmp_t == 0x00000001){
+		tmp = reg32_read(DDRC_STAT(0));
+		tmp_t = tmp && 0x00000001;
+	}
+
+	reg32_write(DDRC_MSTR(0), 0x83040010); /* Two ranks */
+
+	reg32_write(DDRC_MRCTRL0(0), 0x40007030);
+	reg32_write(DDRC_MRCTRL1(0), 0x000170df);
+	reg32_write(DDRC_MRCTRL2(0), 0x97d37be3);
+	reg32_write(DDRC_DERATEEN(0), 0x00000302);
+	reg32_write(DDRC_DERATEINT(0), 0xbc808cc7);
+	reg32_write(DDRC_MSTR2(0), 0x00000001);
+	reg32_write(DDRC_PWRCTL(0), 0x000001ae);
+	reg32_write(DDRC_PWRTMG(0), 0x000d2800);
+	reg32_write(DDRC_HWLPCTL(0), 0x000c0000);
+	reg32_write(DDRC_HWFFCCTL(0), 0x00000010);
+	reg32_write(DDRC_RFSHCTL0(0), 0x007090b0);
+	reg32_write(DDRC_RFSHCTL1(0), 0x00420019);
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000010);
+	reg32_write(DDRC_RFSHTMG(0), 0x0049009d);
+	reg32_write(DDRC_CRCPARCTL0(0), 0x00000000);
+	reg32_write(DDRC_CRCPARCTL1(0), 0x00001011);
+	reg32_write(DDRC_INIT0(0), 0xc0030002);
+	reg32_write(DDRC_INIT1(0), 0x00030006);
+	reg32_write(DDRC_INIT2(0), 0x00000305);
+	reg32_write(DDRC_INIT3(0), 0x0a300001);
+	reg32_write(DDRC_INIT4(0), 0x10180240);
+	reg32_write(DDRC_INIT5(0), 0x0011008a);
+	reg32_write(DDRC_INIT6(0), 0x0a000042);
+	reg32_write(DDRC_INIT7(0), 0x00000800);
+	reg32_write(DDRC_DIMMCTL(0), 0x00000032); /* [1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram. */
+	reg32_write(DDRC_RANKCTL(0), 0x00000530);
+	reg32_write(DDRC_DRAMTMG0(0), 0x14132813);
+	reg32_write(DDRC_DRAMTMG1(0), 0x0007051b);
+	reg32_write(DDRC_DRAMTMG2(0), 0x090a050f);
+	reg32_write(DDRC_DRAMTMG3(0), 0x0000f00f);
+	reg32_write(DDRC_DRAMTMG4(0), 0x08030409);
+	reg32_write(DDRC_DRAMTMG5(0), 0x0c0d0504);
+	reg32_write(DDRC_DRAMTMG6(0), 0x00000003);
+	reg32_write(DDRC_DRAMTMG7(0), 0x00000d0c);
+	reg32_write(DDRC_DRAMTMG8(0), 0x05051f09);
+	reg32_write(DDRC_DRAMTMG9(0), 0x0002040c);
+	reg32_write(DDRC_DRAMTMG10(0), 0x000e0d0b);
+	reg32_write(DDRC_DRAMTMG11(0), 0x1409011e);
+	reg32_write(DDRC_DRAMTMG12(0), 0x0000000d);
+	reg32_write(DDRC_DRAMTMG13(0), 0x09000000);
+	reg32_write(DDRC_DRAMTMG14(0), 0x00000371);
+	reg32_write(DDRC_DRAMTMG15(0), 0x80000000);
+	reg32_write(DDRC_DRAMTMG17(0), 0x0076006e);
+	reg32_write(DDRC_ZQCTL0(0), 0x51000040);
+	reg32_write(DDRC_ZQCTL1(0), 0x00000070);
+	reg32_write(DDRC_ZQCTL2(0), 0x00000000);
+	reg32_write(DDRC_DFITMG0(0), 0x038f820c);
+	reg32_write(DDRC_DFITMG1(0), 0x00020103);
+	reg32_write(DDRC_DFILPCFG0(0), 0x07e1b011);
+	reg32_write(DDRC_DFILPCFG1(0), 0x00000030);
+	reg32_write(DDRC_DFIUPD0(0), 0xe0400018);
+	reg32_write(DDRC_DFIUPD1(0), 0x004e00c3);
+	reg32_write(DDRC_DFIUPD2(0), 0x00000000);
+	reg32_write(DDRC_DFIMISC(0), 0x00000001);
+	reg32_write(DDRC_DFITMG2(0), 0x00000f0c);
+	reg32_write(DDRC_DFITMG3(0), 0x00000001);
+	reg32_write(DDRC_DBICTL(0), 0x00000000);
+	reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000);
+
+	reg32_write(DDRC_ADDRMAP0(0), 0x00001F17); /* [4:0]cs0: 6+23 */
+	reg32_write(DDRC_ADDRMAP1(0), 0x003F0808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+, unused */
+	reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2;  [11:8] col-b3: 3+0; [19:16] col-b4: 4+0 ; [27:24] col-b5: 5+0 */
+	reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6+0;  [11:8] col-b7: 7+0; [19:16] col-b8: 8+0 ; [27:24] col-b9: 9+0 */
+	reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */
+	reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6+7;  [11:8] row-b1: 7+7; [19:16] row-b2_b10: 8~16+7; [27:24] row-b11: 17+7 */
+	reg32_write(DDRC_ADDRMAP6(0), 0x07070707); /* [3:0] row-b12:18+7; [11:8] row-b13: 19+7; [19:16] row-b14:20+7 */
+	reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); /* col-b10, col-b11 not used */
+	reg32_write(DDRC_ADDRMAP8(0), 0x00003F0A); /* [5:0] bg-b0: 2+10; [13:8]bg-b1:3+, unused */
+	reg32_write(DDRC_ADDRMAP9(0), 0x00000000); /*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	reg32_write(DDRC_ADDRMAP10(0), 0x00000000);/*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	reg32_write(DDRC_ADDRMAP11(0), 0x00000000);
+
+
+	reg32_write(DDRC_ODTCFG(0), 0x05170558);
+	reg32_write(DDRC_ODTMAP(0), 0x00002113);
+	reg32_write(DDRC_SCHED(0), 0x0d6f0705);
+	reg32_write(DDRC_SCHED1(0), 0x00000000);
+	reg32_write(DDRC_PERFHPR1(0), 0xe500558b);
+	reg32_write(DDRC_PERFLPR1(0), 0x75001fea);
+	reg32_write(DDRC_PERFWR1(0), 0x880026c7);
+	reg32_write(DDRC_DBG0(0), 0x00000011);
+	reg32_write(DDRC_DBG1(0), 0x00000000);
+	reg32_write(DDRC_DBGCMD(0), 0x00000000);
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+	reg32_write(DDRC_POISONCFG(0), 0x00100011);
+	reg32_write(DDRC_PCCFG(0), 0x00000100);
+	reg32_write(DDRC_PCFGR_0(0), 0x00015313);
+	reg32_write(DDRC_PCFGW_0(0), 0x000050dc);
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+	reg32_write(DDRC_PCFGQOS0_0(0), 0x01100200);
+	reg32_write(DDRC_PCFGQOS1_0(0), 0x01ba023a);
+	reg32_write(DDRC_PCFGWQOS0_0(0), 0x00110000);
+	reg32_write(DDRC_PCFGWQOS1_0(0), 0x0000001e);
+}
+
+int ddr_init(struct dram_timing_info *timing_info)
+{
+	/* change the clock source of dram_apb_clk_root  */
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+		     CLK_ROOT_SOURCE_SEL(4) |
+		     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
+
+	/* disable the clock gating */
+	reg32_write(0x303A00EC,0x0000ffff);
+	reg32setbit(0x303A00F8,5);
+	reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
+
+	dram_pll_init(MHZ(600));
+
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+
+	/* Configure uMCTL2's registers */
+	umctl2_cfg();
+
+	tmp = reg32_read(DDRC_RFSHCTL3(0));
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
+
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+
+	ddr_load_train_code(FW_1D_IMAGE);
+
+	reg32_write(DDRC_DBG1(0), 0x00000000);
+	tmp = reg32_read(DDRC_PWRCTL(0));
+	reg32_write(DDRC_PWRCTL(0), 0x000001ae);
+	tmp = reg32_read(DDRC_PWRCTL(0));
+	reg32_write(DDRC_PWRCTL(0), 0x000001ac);
+	reg32_write(DDRC_SWCTL(0), 0x00000000);
+	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+	reg32_write(DDRC_DFIMISC(0), 0x00000000);
+	reg32_write(DDRC_DFIMISC(0), 0x00000000);
+
+	tmp = reg32_read(DDRC_DBICTL(0));
+	tmp = reg32_read(DDRC_MSTR(0));
+	tmp = reg32_read(DDRC_INIT3(0));
+	tmp = reg32_read(DDRC_INIT4(0));
+	tmp = reg32_read(DDRC_INIT6(0));
+	tmp = reg32_read(DDRC_INIT7(0));
+	tmp = reg32_read(DDRC_INIT0(0));
+
+	ddr4_phyinit_train_2400mts();
+
+	do {
+		tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*0x00020097);
+	} while (tmp_t != 0);
+
+
+	reg32_write(DDRC_DFIMISC(0), 0x00000020);
+
+	/*  wait DFISTAT.dfi_init_complete to 1 */
+	tmp_t = 0;
+	while(tmp_t == 0){
+		tmp  = reg32_read(DDRC_DFISTAT(0));
+		tmp_t = tmp & 0x01;
+	}
+
+	/*  clear DFIMISC.dfi_init_complete_en */
+	reg32_write(DDRC_DFIMISC(0), 0x00000000);
+	/*  set DFIMISC.dfi_init_complete_en again */
+	reg32_write(DDRC_DFIMISC(0), 0x00000001);
+	reg32_write(DDRC_PWRCTL(0), 0x0000018c);
+
+	/*  set SWCTL.sw_done to enable quasi-dynamic register programming outside reset .*/
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+	/* wait SWSTAT.sw_done_ack to 1 */
+	tmp_t = 0;
+	while(tmp_t==0){
+		tmp  = reg32_read(DDRC_SWSTAT(0));
+		tmp_t = tmp & 0x01;
+	}
+
+	/* wait STAT to normal state */
+	tmp_t = 0;
+	while(tmp_t==0){
+		tmp  = reg32_read(DDRC_STAT(0));
+		tmp_t = tmp & 0x01;
+	}
+
+	tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+	reg32_write(DDRC_PWRCTL(0), 0x0000018c);
+
+	reg32_write(DDRC_DERATEEN(0), 0x00000302);
+
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000010); /*  dis_auto-refresh is set to 0 */
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0xd0000), 0);
+	tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54030));
+	tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54035));
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0xd0000), 1);
+	return 0;
+}
diff --git a/board/freescale/imx8mq_val/ddr/ddr4/ddrphy_train.c b/board/freescale/imx8mq_val/ddr/ddr4/ddrphy_train.c
new file mode 100644
index 00000000000..25593248cee
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/ddr4/ddrphy_train.c
@@ -0,0 +1,1362 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include "../ddr.h"
+
+#define DDR_RON 2
+#define PHY_RTT 48
+#define PHYREF_VALUE 0x3b
+
+#define PHY_RON 40
+#define DDR_RTT 5
+#define MR6_VALUE 0x1f
+
+void ddr4_phyinit_train_2400mts(){
+	dwc_ddrphy_apb_wr(0x1005f,0x2ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1015f,0x2ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1105f,0x2ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1115f,0x2ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1205f,0x2ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1215f,0x2ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1305f,0x2ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1315f,0x2ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */
+
+	dwc_ddrphy_apb_wr(0x55,0x3ff); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x1055,0x3ff); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x2055,0x3ff); /* DWC_DDRPHYA_ANIB2_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x3055,0x3ff); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x4055,0xff); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x5055,0xff); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x6055,0x3ff); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x7055,0x3ff); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x8055,0x3ff); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */
+
+	dwc_ddrphy_apb_wr(0x9055,0x3ff); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x200c5,0xa); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */
+	dwc_ddrphy_apb_wr(0x2002e,0x2); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */
+	dwc_ddrphy_apb_wr(0x20024,0x9); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */
+	dwc_ddrphy_apb_wr(0x2003a,0x2); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
+	dwc_ddrphy_apb_wr(0x20056,0x2); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */
+	dwc_ddrphy_apb_wr(0x1004d,0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1014d,0x1a); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1104d,0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1114d,0x1a); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1204d,0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1214d,0x1a); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1304d,0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1314d,0x1a); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x10049,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x10149,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x11049,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x11149,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x12049,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x12149,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x13049,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x13149,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x43,0x3ff); /* DWC_DDRPHYA_ANIB0_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x1043,0x3ff); /* DWC_DDRPHYA_ANIB1_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x2043,0x3ff); /* DWC_DDRPHYA_ANIB2_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x3043,0x3ff); /* DWC_DDRPHYA_ANIB3_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x4043,0x3ff); /* DWC_DDRPHYA_ANIB4_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x5043,0x3ff); /* DWC_DDRPHYA_ANIB5_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x6043,0x3ff); /* DWC_DDRPHYA_ANIB6_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x7043,0x3ff); /* DWC_DDRPHYA_ANIB7_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x8043,0x3ff); /* DWC_DDRPHYA_ANIB8_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x9043,0x3ff); /* DWC_DDRPHYA_ANIB9_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x20018,0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */
+	dwc_ddrphy_apb_wr(0x20075,0x2); /* DWC_DDRPHYA_MASTER0_DfiCAMode */
+	dwc_ddrphy_apb_wr(0x20050,0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */
+	dwc_ddrphy_apb_wr(0x20008,0x258); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */
+	dwc_ddrphy_apb_wr(0x20088,0x9); /* DWC_DDRPHYA_MASTER0_CalRate */
+	dwc_ddrphy_apb_wr(0x200b2,0x288); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */
+	dwc_ddrphy_apb_wr(0x10043,0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x10143,0x5b1); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x11043,0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x11143,0x5b1); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x12043,0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x12143,0x5b1); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x13043,0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x13143,0x5b1); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x200fa,0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */
+	dwc_ddrphy_apb_wr(0x20019,0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */
+	dwc_ddrphy_apb_wr(0x200f0,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
+	dwc_ddrphy_apb_wr(0x200f1,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */
+	dwc_ddrphy_apb_wr(0x200f2,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */
+	dwc_ddrphy_apb_wr(0x200f3,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */
+	dwc_ddrphy_apb_wr(0x200f4,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */
+	dwc_ddrphy_apb_wr(0x200f5,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */
+	dwc_ddrphy_apb_wr(0x200f6,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */
+	dwc_ddrphy_apb_wr(0x200f7,0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */
+	dwc_ddrphy_apb_wr(0x2000b,0x4c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
+	dwc_ddrphy_apb_wr(0x2000c,0x97); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
+	dwc_ddrphy_apb_wr(0x2000d,0x5dd); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
+	dwc_ddrphy_apb_wr(0x2000e,0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
+	dwc_ddrphy_apb_wr(0x20025,0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */
+	dwc_ddrphy_apb_wr(0x2002d,0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */
+	dwc_ddrphy_apb_wr(0x20060,0x2); /* DWC_DDRPHYA_MASTER0_MemResetL */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0x54000,0x80);/* should be 0x80 in silicon */
+	dwc_ddrphy_apb_wr(0x54001,0x0);
+	dwc_ddrphy_apb_wr(0x54002,0x0);
+	dwc_ddrphy_apb_wr(0x54003,0x960);
+	dwc_ddrphy_apb_wr(0x54004,0x2);
+
+	dwc_ddrphy_apb_wr(0x54005,((PHY_RON<<8)|(PHY_RTT<<0))/*0x2830*/);
+	dwc_ddrphy_apb_wr(0x54006,(0x200|PHYREF_VALUE)/*0x23b*/);
+	dwc_ddrphy_apb_wr(0x54007,0x2000);
+
+	dwc_ddrphy_apb_wr(0x54008,0x303); /* Two ranks */
+
+	dwc_ddrphy_apb_wr(0x54009,0x200);/* no addr mirror, 0x200 addr mirror */
+	dwc_ddrphy_apb_wr(0x5400a,0x0);
+	dwc_ddrphy_apb_wr(0x5400b,0x31f);/* should be 0x31f in silicon */
+
+	dwc_ddrphy_apb_wr(0x5400c,0xc8); /* 0xc8 indicates stage completion messages showed */
+
+	dwc_ddrphy_apb_wr(0x5400d,0x0);
+	dwc_ddrphy_apb_wr(0x5400e,0x0);
+	dwc_ddrphy_apb_wr(0x5400f,0x0);
+	dwc_ddrphy_apb_wr(0x54010,0x0);
+	dwc_ddrphy_apb_wr(0x54011,0x0);
+	dwc_ddrphy_apb_wr(0x54012,0x1);
+	dwc_ddrphy_apb_wr(0x54013,0x0);
+	dwc_ddrphy_apb_wr(0x54014,0x0);
+	dwc_ddrphy_apb_wr(0x54015,0x0);
+	dwc_ddrphy_apb_wr(0x54016,0x0);
+	dwc_ddrphy_apb_wr(0x54017,0x0);
+	dwc_ddrphy_apb_wr(0x54018,0x0);
+	dwc_ddrphy_apb_wr(0x54019,0x0);
+	dwc_ddrphy_apb_wr(0x5401a,0x0);
+	dwc_ddrphy_apb_wr(0x5401b,0x0);
+	dwc_ddrphy_apb_wr(0x5401c,0x0);
+	dwc_ddrphy_apb_wr(0x5401d,0x0);
+	dwc_ddrphy_apb_wr(0x5401e,0x0);
+	dwc_ddrphy_apb_wr(0x5401f,0x0);
+	dwc_ddrphy_apb_wr(0x54020,0x0);
+	dwc_ddrphy_apb_wr(0x54021,0x0);
+	dwc_ddrphy_apb_wr(0x54022,0x0);
+	dwc_ddrphy_apb_wr(0x54023,0x0);
+	dwc_ddrphy_apb_wr(0x54024,0x0);
+	dwc_ddrphy_apb_wr(0x54025,0x0);
+	dwc_ddrphy_apb_wr(0x54026,0x0);
+	dwc_ddrphy_apb_wr(0x54027,0x0);
+	dwc_ddrphy_apb_wr(0x54028,0x0);
+	dwc_ddrphy_apb_wr(0x54029,0x0);
+	dwc_ddrphy_apb_wr(0x5402a,0x0);
+	dwc_ddrphy_apb_wr(0x5402b,0x0);
+	dwc_ddrphy_apb_wr(0x5402c,0x0);
+	dwc_ddrphy_apb_wr(0x5402d,0x0);
+	dwc_ddrphy_apb_wr(0x5402e,0x0);
+
+	dwc_ddrphy_apb_wr(0x5402f,0xa30);/* MR0 */
+	dwc_ddrphy_apb_wr(0x54030, ((DDR_RTT<<8)|(DDR_RON<<1)|0x1)/*0x1*/);/* MR1 */
+	dwc_ddrphy_apb_wr(0x54031,0x1018);/* MR2 */
+	dwc_ddrphy_apb_wr(0x54032,0x240);/* MR3 */
+	dwc_ddrphy_apb_wr(0x54033,0xa00);/* MR4 */
+	dwc_ddrphy_apb_wr(0x54034,0x42);/* MR5 */
+	dwc_ddrphy_apb_wr(0x54035,(0x800|MR6_VALUE)/*0x800*/);/* MR6 */
+
+	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54030));
+	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4*(0x54035));
+
+	dwc_ddrphy_apb_wr(0x54036,0x103);
+	dwc_ddrphy_apb_wr(0x54037,0x0);
+	dwc_ddrphy_apb_wr(0x54038,0x0);
+	dwc_ddrphy_apb_wr(0x54039,0x0);
+	dwc_ddrphy_apb_wr(0x5403a,0x0);
+	dwc_ddrphy_apb_wr(0x5403b,0x0);
+	dwc_ddrphy_apb_wr(0x5403c,0x0);
+	dwc_ddrphy_apb_wr(0x5403d,0x0);
+	dwc_ddrphy_apb_wr(0x5403e,0x0);
+	dwc_ddrphy_apb_wr(0x5403f,0x1221);
+	dwc_ddrphy_apb_wr(0x54040,0x0);
+	dwc_ddrphy_apb_wr(0x54041,0x0);
+	dwc_ddrphy_apb_wr(0x54042,0x0);
+	dwc_ddrphy_apb_wr(0x54043,0x0);
+	dwc_ddrphy_apb_wr(0x54044,0x0);
+	dwc_ddrphy_apb_wr(0x54045,0x0);
+	dwc_ddrphy_apb_wr(0x54046,0x0);
+	dwc_ddrphy_apb_wr(0x54047,0x0);
+	dwc_ddrphy_apb_wr(0x54048,0x0);
+	dwc_ddrphy_apb_wr(0x54049,0x0);
+	dwc_ddrphy_apb_wr(0x5404a,0x0);
+	dwc_ddrphy_apb_wr(0x5404b,0x0);
+	dwc_ddrphy_apb_wr(0x5404c,0x0);
+	dwc_ddrphy_apb_wr(0x5404d,0x0);
+	dwc_ddrphy_apb_wr(0x5404e,0x0);
+	dwc_ddrphy_apb_wr(0x5404f,0x0);
+	dwc_ddrphy_apb_wr(0x54050,0x0);
+	dwc_ddrphy_apb_wr(0x54051,0x0);
+	dwc_ddrphy_apb_wr(0x54052,0x0);
+	dwc_ddrphy_apb_wr(0x54053,0x0);
+	dwc_ddrphy_apb_wr(0x54054,0x0);
+	dwc_ddrphy_apb_wr(0x54055,0x0);
+	dwc_ddrphy_apb_wr(0x54056,0x0);
+	dwc_ddrphy_apb_wr(0x54057,0x0);
+	dwc_ddrphy_apb_wr(0x54058,0x0);
+	dwc_ddrphy_apb_wr(0x54059,0x0);
+	dwc_ddrphy_apb_wr(0x5405a,0x0);
+	dwc_ddrphy_apb_wr(0x5405b,0x0);
+	dwc_ddrphy_apb_wr(0x5405c,0x0);
+	dwc_ddrphy_apb_wr(0x5405d,0x0);
+	dwc_ddrphy_apb_wr(0x5405e,0x0);
+	dwc_ddrphy_apb_wr(0x5405f,0x0);
+	dwc_ddrphy_apb_wr(0x54060,0x0);
+	dwc_ddrphy_apb_wr(0x54061,0x0);
+	dwc_ddrphy_apb_wr(0x54062,0x0);
+	dwc_ddrphy_apb_wr(0x54063,0x0);
+	dwc_ddrphy_apb_wr(0x54064,0x0);
+	dwc_ddrphy_apb_wr(0x54065,0x0);
+	dwc_ddrphy_apb_wr(0x54066,0x0);
+	dwc_ddrphy_apb_wr(0x54067,0x0);
+	dwc_ddrphy_apb_wr(0x54068,0x0);
+	dwc_ddrphy_apb_wr(0x54069,0x0);
+	dwc_ddrphy_apb_wr(0x5406a,0x0);
+	dwc_ddrphy_apb_wr(0x5406b,0x0);
+	dwc_ddrphy_apb_wr(0x5406c,0x0);
+	dwc_ddrphy_apb_wr(0x5406d,0x0);
+	dwc_ddrphy_apb_wr(0x5406e,0x0);
+	dwc_ddrphy_apb_wr(0x5406f,0x0);
+	dwc_ddrphy_apb_wr(0x54070,0x0);
+	dwc_ddrphy_apb_wr(0x54071,0x0);
+	dwc_ddrphy_apb_wr(0x54072,0x0);
+	dwc_ddrphy_apb_wr(0x54073,0x0);
+	dwc_ddrphy_apb_wr(0x54074,0x0);
+	dwc_ddrphy_apb_wr(0x54075,0x0);
+	dwc_ddrphy_apb_wr(0x54076,0x0);
+	dwc_ddrphy_apb_wr(0x54077,0x0);
+	dwc_ddrphy_apb_wr(0x54078,0x0);
+	dwc_ddrphy_apb_wr(0x54079,0x0);
+	dwc_ddrphy_apb_wr(0x5407a,0x0);
+	dwc_ddrphy_apb_wr(0x5407b,0x0);
+	dwc_ddrphy_apb_wr(0x5407c,0x0);
+	dwc_ddrphy_apb_wr(0x5407d,0x0);
+	dwc_ddrphy_apb_wr(0x5407e,0x0);
+	dwc_ddrphy_apb_wr(0x5407f,0x0);
+	dwc_ddrphy_apb_wr(0x54080,0x0);
+	dwc_ddrphy_apb_wr(0x54081,0x0);
+	dwc_ddrphy_apb_wr(0x54082,0x0);
+	dwc_ddrphy_apb_wr(0x54083,0x0);
+	dwc_ddrphy_apb_wr(0x54084,0x0);
+	dwc_ddrphy_apb_wr(0x54085,0x0);
+	dwc_ddrphy_apb_wr(0x54086,0x0);
+	dwc_ddrphy_apb_wr(0x54087,0x0);
+	dwc_ddrphy_apb_wr(0x54088,0x0);
+	dwc_ddrphy_apb_wr(0x54089,0x0);
+	dwc_ddrphy_apb_wr(0x5408a,0x0);
+	dwc_ddrphy_apb_wr(0x5408b,0x0);
+	dwc_ddrphy_apb_wr(0x5408c,0x0);
+	dwc_ddrphy_apb_wr(0x5408d,0x0);
+	dwc_ddrphy_apb_wr(0x5408e,0x0);
+	dwc_ddrphy_apb_wr(0x5408f,0x0);
+	dwc_ddrphy_apb_wr(0x54090,0x0);
+	dwc_ddrphy_apb_wr(0x54091,0x0);
+	dwc_ddrphy_apb_wr(0x54092,0x0);
+	dwc_ddrphy_apb_wr(0x54093,0x0);
+	dwc_ddrphy_apb_wr(0x54094,0x0);
+	dwc_ddrphy_apb_wr(0x54095,0x0);
+	dwc_ddrphy_apb_wr(0x54096,0x0);
+	dwc_ddrphy_apb_wr(0x54097,0x0);
+	dwc_ddrphy_apb_wr(0x54098,0x0);
+	dwc_ddrphy_apb_wr(0x54099,0x0);
+	dwc_ddrphy_apb_wr(0x5409a,0x0);
+	dwc_ddrphy_apb_wr(0x5409b,0x0);
+	dwc_ddrphy_apb_wr(0x5409c,0x0);
+	dwc_ddrphy_apb_wr(0x5409d,0x0);
+	dwc_ddrphy_apb_wr(0x5409e,0x0);
+	dwc_ddrphy_apb_wr(0x5409f,0x0);
+	dwc_ddrphy_apb_wr(0x540a0,0x0);
+	dwc_ddrphy_apb_wr(0x540a1,0x0);
+	dwc_ddrphy_apb_wr(0x540a2,0x0);
+	dwc_ddrphy_apb_wr(0x540a3,0x0);
+	dwc_ddrphy_apb_wr(0x540a4,0x0);
+	dwc_ddrphy_apb_wr(0x540a5,0x0);
+	dwc_ddrphy_apb_wr(0x540a6,0x0);
+	dwc_ddrphy_apb_wr(0x540a7,0x0);
+	dwc_ddrphy_apb_wr(0x540a8,0x0);
+	dwc_ddrphy_apb_wr(0x540a9,0x0);
+	dwc_ddrphy_apb_wr(0x540aa,0x0);
+	dwc_ddrphy_apb_wr(0x540ab,0x0);
+	dwc_ddrphy_apb_wr(0x540ac,0x0);
+	dwc_ddrphy_apb_wr(0x540ad,0x0);
+	dwc_ddrphy_apb_wr(0x540ae,0x0);
+	dwc_ddrphy_apb_wr(0x540af,0x0);
+	dwc_ddrphy_apb_wr(0x540b0,0x0);
+	dwc_ddrphy_apb_wr(0x540b1,0x0);
+	dwc_ddrphy_apb_wr(0x540b2,0x0);
+	dwc_ddrphy_apb_wr(0x540b3,0x0);
+	dwc_ddrphy_apb_wr(0x540b4,0x0);
+	dwc_ddrphy_apb_wr(0x540b5,0x0);
+	dwc_ddrphy_apb_wr(0x540b6,0x0);
+	dwc_ddrphy_apb_wr(0x540b7,0x0);
+	dwc_ddrphy_apb_wr(0x540b8,0x0);
+	dwc_ddrphy_apb_wr(0x540b9,0x0);
+	dwc_ddrphy_apb_wr(0x540ba,0x0);
+	dwc_ddrphy_apb_wr(0x540bb,0x0);
+	dwc_ddrphy_apb_wr(0x540bc,0x0);
+	dwc_ddrphy_apb_wr(0x540bd,0x0);
+	dwc_ddrphy_apb_wr(0x540be,0x0);
+	dwc_ddrphy_apb_wr(0x540bf,0x0);
+	dwc_ddrphy_apb_wr(0x540c0,0x0);
+	dwc_ddrphy_apb_wr(0x540c1,0x0);
+	dwc_ddrphy_apb_wr(0x540c2,0x0);
+	dwc_ddrphy_apb_wr(0x540c3,0x0);
+	dwc_ddrphy_apb_wr(0x540c4,0x0);
+	dwc_ddrphy_apb_wr(0x540c5,0x0);
+	dwc_ddrphy_apb_wr(0x540c6,0x0);
+	dwc_ddrphy_apb_wr(0x540c7,0x0);
+	dwc_ddrphy_apb_wr(0x540c8,0x0);
+	dwc_ddrphy_apb_wr(0x540c9,0x0);
+	dwc_ddrphy_apb_wr(0x540ca,0x0);
+	dwc_ddrphy_apb_wr(0x540cb,0x0);
+	dwc_ddrphy_apb_wr(0x540cc,0x0);
+	dwc_ddrphy_apb_wr(0x540cd,0x0);
+	dwc_ddrphy_apb_wr(0x540ce,0x0);
+	dwc_ddrphy_apb_wr(0x540cf,0x0);
+	dwc_ddrphy_apb_wr(0x540d0,0x0);
+	dwc_ddrphy_apb_wr(0x540d1,0x0);
+	dwc_ddrphy_apb_wr(0x540d2,0x0);
+	dwc_ddrphy_apb_wr(0x540d3,0x0);
+	dwc_ddrphy_apb_wr(0x540d4,0x0);
+	dwc_ddrphy_apb_wr(0x540d5,0x0);
+	dwc_ddrphy_apb_wr(0x540d6,0x0);
+	dwc_ddrphy_apb_wr(0x540d7,0x0);
+	dwc_ddrphy_apb_wr(0x540d8,0x0);
+	dwc_ddrphy_apb_wr(0x540d9,0x0);
+	dwc_ddrphy_apb_wr(0x540da,0x0);
+	dwc_ddrphy_apb_wr(0x540db,0x0);
+	dwc_ddrphy_apb_wr(0x540dc,0x0);
+	dwc_ddrphy_apb_wr(0x540dd,0x0);
+	dwc_ddrphy_apb_wr(0x540de,0x0);
+	dwc_ddrphy_apb_wr(0x540df,0x0);
+	dwc_ddrphy_apb_wr(0x540e0,0x0);
+	dwc_ddrphy_apb_wr(0x540e1,0x0);
+	dwc_ddrphy_apb_wr(0x540e2,0x0);
+	dwc_ddrphy_apb_wr(0x540e3,0x0);
+	dwc_ddrphy_apb_wr(0x540e4,0x0);
+	dwc_ddrphy_apb_wr(0x540e5,0x0);
+	dwc_ddrphy_apb_wr(0x540e6,0x0);
+	dwc_ddrphy_apb_wr(0x540e7,0x0);
+	dwc_ddrphy_apb_wr(0x540e8,0x0);
+	dwc_ddrphy_apb_wr(0x540e9,0x0);
+	dwc_ddrphy_apb_wr(0x540ea,0x0);
+	dwc_ddrphy_apb_wr(0x540eb,0x0);
+	dwc_ddrphy_apb_wr(0x540ec,0x0);
+	dwc_ddrphy_apb_wr(0x540ed,0x0);
+	dwc_ddrphy_apb_wr(0x540ee,0x0);
+	dwc_ddrphy_apb_wr(0x540ef,0x0);
+	dwc_ddrphy_apb_wr(0x540f0,0x0);
+	dwc_ddrphy_apb_wr(0x540f1,0x0);
+	dwc_ddrphy_apb_wr(0x540f2,0x0);
+	dwc_ddrphy_apb_wr(0x540f3,0x0);
+	dwc_ddrphy_apb_wr(0x540f4,0x0);
+	dwc_ddrphy_apb_wr(0x540f5,0x0);
+	dwc_ddrphy_apb_wr(0x540f6,0x0);
+	dwc_ddrphy_apb_wr(0x540f7,0x0);
+	dwc_ddrphy_apb_wr(0x540f8,0x0);
+	dwc_ddrphy_apb_wr(0x540f9,0x0);
+	dwc_ddrphy_apb_wr(0x540fa,0x0);
+	dwc_ddrphy_apb_wr(0x540fb,0x0);
+	dwc_ddrphy_apb_wr(0x540fc,0x0);
+	dwc_ddrphy_apb_wr(0x540fd,0x0);
+	dwc_ddrphy_apb_wr(0x540fe,0x0);
+	dwc_ddrphy_apb_wr(0x540ff,0x0);
+	dwc_ddrphy_apb_wr(0x54100,0x0);
+	dwc_ddrphy_apb_wr(0x54101,0x0);
+	dwc_ddrphy_apb_wr(0x54102,0x0);
+	dwc_ddrphy_apb_wr(0x54103,0x0);
+	dwc_ddrphy_apb_wr(0x54104,0x0);
+	dwc_ddrphy_apb_wr(0x54105,0x0);
+	dwc_ddrphy_apb_wr(0x54106,0x0);
+	dwc_ddrphy_apb_wr(0x54107,0x0);
+	dwc_ddrphy_apb_wr(0x54108,0x0);
+	dwc_ddrphy_apb_wr(0x54109,0x0);
+	dwc_ddrphy_apb_wr(0x5410a,0x0);
+	dwc_ddrphy_apb_wr(0x5410b,0x0);
+	dwc_ddrphy_apb_wr(0x5410c,0x0);
+	dwc_ddrphy_apb_wr(0x5410d,0x0);
+	dwc_ddrphy_apb_wr(0x5410e,0x0);
+	dwc_ddrphy_apb_wr(0x5410f,0x0);
+	dwc_ddrphy_apb_wr(0x54110,0x0);
+	dwc_ddrphy_apb_wr(0x54111,0x0);
+	dwc_ddrphy_apb_wr(0x54112,0x0);
+	dwc_ddrphy_apb_wr(0x54113,0x0);
+	dwc_ddrphy_apb_wr(0x54114,0x0);
+	dwc_ddrphy_apb_wr(0x54115,0x0);
+	dwc_ddrphy_apb_wr(0x54116,0x0);
+	dwc_ddrphy_apb_wr(0x54117,0x0);
+	dwc_ddrphy_apb_wr(0x54118,0x0);
+	dwc_ddrphy_apb_wr(0x54119,0x0);
+	dwc_ddrphy_apb_wr(0x5411a,0x0);
+	dwc_ddrphy_apb_wr(0x5411b,0x0);
+	dwc_ddrphy_apb_wr(0x5411c,0x0);
+	dwc_ddrphy_apb_wr(0x5411d,0x0);
+	dwc_ddrphy_apb_wr(0x5411e,0x0);
+	dwc_ddrphy_apb_wr(0x5411f,0x0);
+	dwc_ddrphy_apb_wr(0x54120,0x0);
+	dwc_ddrphy_apb_wr(0x54121,0x0);
+	dwc_ddrphy_apb_wr(0x54122,0x0);
+	dwc_ddrphy_apb_wr(0x54123,0x0);
+	dwc_ddrphy_apb_wr(0x54124,0x0);
+	dwc_ddrphy_apb_wr(0x54125,0x0);
+	dwc_ddrphy_apb_wr(0x54126,0x0);
+	dwc_ddrphy_apb_wr(0x54127,0x0);
+	dwc_ddrphy_apb_wr(0x54128,0x0);
+	dwc_ddrphy_apb_wr(0x54129,0x0);
+	dwc_ddrphy_apb_wr(0x5412a,0x0);
+	dwc_ddrphy_apb_wr(0x5412b,0x0);
+	dwc_ddrphy_apb_wr(0x5412c,0x0);
+	dwc_ddrphy_apb_wr(0x5412d,0x0);
+	dwc_ddrphy_apb_wr(0x5412e,0x0);
+	dwc_ddrphy_apb_wr(0x5412f,0x0);
+	dwc_ddrphy_apb_wr(0x54130,0x0);
+	dwc_ddrphy_apb_wr(0x54131,0x0);
+	dwc_ddrphy_apb_wr(0x54132,0x0);
+	dwc_ddrphy_apb_wr(0x54133,0x0);
+	dwc_ddrphy_apb_wr(0x54134,0x0);
+	dwc_ddrphy_apb_wr(0x54135,0x0);
+	dwc_ddrphy_apb_wr(0x54136,0x0);
+	dwc_ddrphy_apb_wr(0x54137,0x0);
+	dwc_ddrphy_apb_wr(0x54138,0x0);
+	dwc_ddrphy_apb_wr(0x54139,0x0);
+	dwc_ddrphy_apb_wr(0x5413a,0x0);
+	dwc_ddrphy_apb_wr(0x5413b,0x0);
+	dwc_ddrphy_apb_wr(0x5413c,0x0);
+	dwc_ddrphy_apb_wr(0x5413d,0x0);
+	dwc_ddrphy_apb_wr(0x5413e,0x0);
+	dwc_ddrphy_apb_wr(0x5413f,0x0);
+	dwc_ddrphy_apb_wr(0x54140,0x0);
+	dwc_ddrphy_apb_wr(0x54141,0x0);
+	dwc_ddrphy_apb_wr(0x54142,0x0);
+	dwc_ddrphy_apb_wr(0x54143,0x0);
+	dwc_ddrphy_apb_wr(0x54144,0x0);
+	dwc_ddrphy_apb_wr(0x54145,0x0);
+	dwc_ddrphy_apb_wr(0x54146,0x0);
+	dwc_ddrphy_apb_wr(0x54147,0x0);
+	dwc_ddrphy_apb_wr(0x54148,0x0);
+	dwc_ddrphy_apb_wr(0x54149,0x0);
+	dwc_ddrphy_apb_wr(0x5414a,0x0);
+	dwc_ddrphy_apb_wr(0x5414b,0x0);
+	dwc_ddrphy_apb_wr(0x5414c,0x0);
+	dwc_ddrphy_apb_wr(0x5414d,0x0);
+	dwc_ddrphy_apb_wr(0x5414e,0x0);
+	dwc_ddrphy_apb_wr(0x5414f,0x0);
+	dwc_ddrphy_apb_wr(0x54150,0x0);
+	dwc_ddrphy_apb_wr(0x54151,0x0);
+	dwc_ddrphy_apb_wr(0x54152,0x0);
+	dwc_ddrphy_apb_wr(0x54153,0x0);
+	dwc_ddrphy_apb_wr(0x54154,0x0);
+	dwc_ddrphy_apb_wr(0x54155,0x0);
+	dwc_ddrphy_apb_wr(0x54156,0x0);
+	dwc_ddrphy_apb_wr(0x54157,0x0);
+	dwc_ddrphy_apb_wr(0x54158,0x0);
+	dwc_ddrphy_apb_wr(0x54159,0x0);
+	dwc_ddrphy_apb_wr(0x5415a,0x0);
+	dwc_ddrphy_apb_wr(0x5415b,0x0);
+	dwc_ddrphy_apb_wr(0x5415c,0x0);
+	dwc_ddrphy_apb_wr(0x5415d,0x0);
+	dwc_ddrphy_apb_wr(0x5415e,0x0);
+	dwc_ddrphy_apb_wr(0x5415f,0x0);
+	dwc_ddrphy_apb_wr(0x54160,0x0);
+	dwc_ddrphy_apb_wr(0x54161,0x0);
+	dwc_ddrphy_apb_wr(0x54162,0x0);
+	dwc_ddrphy_apb_wr(0x54163,0x0);
+	dwc_ddrphy_apb_wr(0x54164,0x0);
+	dwc_ddrphy_apb_wr(0x54165,0x0);
+	dwc_ddrphy_apb_wr(0x54166,0x0);
+	dwc_ddrphy_apb_wr(0x54167,0x0);
+	dwc_ddrphy_apb_wr(0x54168,0x0);
+	dwc_ddrphy_apb_wr(0x54169,0x0);
+	dwc_ddrphy_apb_wr(0x5416a,0x0);
+	dwc_ddrphy_apb_wr(0x5416b,0x0);
+	dwc_ddrphy_apb_wr(0x5416c,0x0);
+	dwc_ddrphy_apb_wr(0x5416d,0x0);
+	dwc_ddrphy_apb_wr(0x5416e,0x0);
+	dwc_ddrphy_apb_wr(0x5416f,0x0);
+	dwc_ddrphy_apb_wr(0x54170,0x0);
+	dwc_ddrphy_apb_wr(0x54171,0x0);
+	dwc_ddrphy_apb_wr(0x54172,0x0);
+	dwc_ddrphy_apb_wr(0x54173,0x0);
+	dwc_ddrphy_apb_wr(0x54174,0x0);
+	dwc_ddrphy_apb_wr(0x54175,0x0);
+	dwc_ddrphy_apb_wr(0x54176,0x0);
+	dwc_ddrphy_apb_wr(0x54177,0x0);
+	dwc_ddrphy_apb_wr(0x54178,0x0);
+	dwc_ddrphy_apb_wr(0x54179,0x0);
+	dwc_ddrphy_apb_wr(0x5417a,0x0);
+	dwc_ddrphy_apb_wr(0x5417b,0x0);
+	dwc_ddrphy_apb_wr(0x5417c,0x0);
+	dwc_ddrphy_apb_wr(0x5417d,0x0);
+	dwc_ddrphy_apb_wr(0x5417e,0x0);
+	dwc_ddrphy_apb_wr(0x5417f,0x0);
+	dwc_ddrphy_apb_wr(0x54180,0x0);
+	dwc_ddrphy_apb_wr(0x54181,0x0);
+	dwc_ddrphy_apb_wr(0x54182,0x0);
+	dwc_ddrphy_apb_wr(0x54183,0x0);
+	dwc_ddrphy_apb_wr(0x54184,0x0);
+	dwc_ddrphy_apb_wr(0x54185,0x0);
+	dwc_ddrphy_apb_wr(0x54186,0x0);
+	dwc_ddrphy_apb_wr(0x54187,0x0);
+	dwc_ddrphy_apb_wr(0x54188,0x0);
+	dwc_ddrphy_apb_wr(0x54189,0x0);
+	dwc_ddrphy_apb_wr(0x5418a,0x0);
+	dwc_ddrphy_apb_wr(0x5418b,0x0);
+	dwc_ddrphy_apb_wr(0x5418c,0x0);
+	dwc_ddrphy_apb_wr(0x5418d,0x0);
+	dwc_ddrphy_apb_wr(0x5418e,0x0);
+	dwc_ddrphy_apb_wr(0x5418f,0x0);
+	dwc_ddrphy_apb_wr(0x54190,0x0);
+	dwc_ddrphy_apb_wr(0x54191,0x0);
+	dwc_ddrphy_apb_wr(0x54192,0x0);
+	dwc_ddrphy_apb_wr(0x54193,0x0);
+	dwc_ddrphy_apb_wr(0x54194,0x0);
+	dwc_ddrphy_apb_wr(0x54195,0x0);
+	dwc_ddrphy_apb_wr(0x54196,0x0);
+	dwc_ddrphy_apb_wr(0x54197,0x0);
+	dwc_ddrphy_apb_wr(0x54198,0x0);
+	dwc_ddrphy_apb_wr(0x54199,0x0);
+	dwc_ddrphy_apb_wr(0x5419a,0x0);
+	dwc_ddrphy_apb_wr(0x5419b,0x0);
+	dwc_ddrphy_apb_wr(0x5419c,0x0);
+	dwc_ddrphy_apb_wr(0x5419d,0x0);
+	dwc_ddrphy_apb_wr(0x5419e,0x0);
+	dwc_ddrphy_apb_wr(0x5419f,0x0);
+	dwc_ddrphy_apb_wr(0x541a0,0x0);
+	dwc_ddrphy_apb_wr(0x541a1,0x0);
+	dwc_ddrphy_apb_wr(0x541a2,0x0);
+	dwc_ddrphy_apb_wr(0x541a3,0x0);
+	dwc_ddrphy_apb_wr(0x541a4,0x0);
+	dwc_ddrphy_apb_wr(0x541a5,0x0);
+	dwc_ddrphy_apb_wr(0x541a6,0x0);
+	dwc_ddrphy_apb_wr(0x541a7,0x0);
+	dwc_ddrphy_apb_wr(0x541a8,0x0);
+	dwc_ddrphy_apb_wr(0x541a9,0x0);
+	dwc_ddrphy_apb_wr(0x541aa,0x0);
+	dwc_ddrphy_apb_wr(0x541ab,0x0);
+	dwc_ddrphy_apb_wr(0x541ac,0x0);
+	dwc_ddrphy_apb_wr(0x541ad,0x0);
+	dwc_ddrphy_apb_wr(0x541ae,0x0);
+	dwc_ddrphy_apb_wr(0x541af,0x0);
+	dwc_ddrphy_apb_wr(0x541b0,0x0);
+	dwc_ddrphy_apb_wr(0x541b1,0x0);
+	dwc_ddrphy_apb_wr(0x541b2,0x0);
+	dwc_ddrphy_apb_wr(0x541b3,0x0);
+	dwc_ddrphy_apb_wr(0x541b4,0x0);
+	dwc_ddrphy_apb_wr(0x541b5,0x0);
+	dwc_ddrphy_apb_wr(0x541b6,0x0);
+	dwc_ddrphy_apb_wr(0x541b7,0x0);
+	dwc_ddrphy_apb_wr(0x541b8,0x0);
+	dwc_ddrphy_apb_wr(0x541b9,0x0);
+	dwc_ddrphy_apb_wr(0x541ba,0x0);
+	dwc_ddrphy_apb_wr(0x541bb,0x0);
+	dwc_ddrphy_apb_wr(0x541bc,0x0);
+	dwc_ddrphy_apb_wr(0x541bd,0x0);
+	dwc_ddrphy_apb_wr(0x541be,0x0);
+	dwc_ddrphy_apb_wr(0x541bf,0x0);
+	dwc_ddrphy_apb_wr(0x541c0,0x0);
+	dwc_ddrphy_apb_wr(0x541c1,0x0);
+	dwc_ddrphy_apb_wr(0x541c2,0x0);
+	dwc_ddrphy_apb_wr(0x541c3,0x0);
+	dwc_ddrphy_apb_wr(0x541c4,0x0);
+	dwc_ddrphy_apb_wr(0x541c5,0x0);
+	dwc_ddrphy_apb_wr(0x541c6,0x0);
+	dwc_ddrphy_apb_wr(0x541c7,0x0);
+	dwc_ddrphy_apb_wr(0x541c8,0x0);
+	dwc_ddrphy_apb_wr(0x541c9,0x0);
+	dwc_ddrphy_apb_wr(0x541ca,0x0);
+	dwc_ddrphy_apb_wr(0x541cb,0x0);
+	dwc_ddrphy_apb_wr(0x541cc,0x0);
+	dwc_ddrphy_apb_wr(0x541cd,0x0);
+	dwc_ddrphy_apb_wr(0x541ce,0x0);
+	dwc_ddrphy_apb_wr(0x541cf,0x0);
+	dwc_ddrphy_apb_wr(0x541d0,0x0);
+	dwc_ddrphy_apb_wr(0x541d1,0x0);
+	dwc_ddrphy_apb_wr(0x541d2,0x0);
+	dwc_ddrphy_apb_wr(0x541d3,0x0);
+	dwc_ddrphy_apb_wr(0x541d4,0x0);
+	dwc_ddrphy_apb_wr(0x541d5,0x0);
+	dwc_ddrphy_apb_wr(0x541d6,0x0);
+	dwc_ddrphy_apb_wr(0x541d7,0x0);
+	dwc_ddrphy_apb_wr(0x541d8,0x0);
+	dwc_ddrphy_apb_wr(0x541d9,0x0);
+	dwc_ddrphy_apb_wr(0x541da,0x0);
+	dwc_ddrphy_apb_wr(0x541db,0x0);
+	dwc_ddrphy_apb_wr(0x541dc,0x0);
+	dwc_ddrphy_apb_wr(0x541dd,0x0);
+	dwc_ddrphy_apb_wr(0x541de,0x0);
+	dwc_ddrphy_apb_wr(0x541df,0x0);
+	dwc_ddrphy_apb_wr(0x541e0,0x0);
+	dwc_ddrphy_apb_wr(0x541e1,0x0);
+	dwc_ddrphy_apb_wr(0x541e2,0x0);
+	dwc_ddrphy_apb_wr(0x541e3,0x0);
+	dwc_ddrphy_apb_wr(0x541e4,0x0);
+	dwc_ddrphy_apb_wr(0x541e5,0x0);
+	dwc_ddrphy_apb_wr(0x541e6,0x0);
+	dwc_ddrphy_apb_wr(0x541e7,0x0);
+	dwc_ddrphy_apb_wr(0x541e8,0x0);
+	dwc_ddrphy_apb_wr(0x541e9,0x0);
+	dwc_ddrphy_apb_wr(0x541ea,0x0);
+	dwc_ddrphy_apb_wr(0x541eb,0x0);
+	dwc_ddrphy_apb_wr(0x541ec,0x0);
+	dwc_ddrphy_apb_wr(0x541ed,0x0);
+	dwc_ddrphy_apb_wr(0x541ee,0x0);
+	dwc_ddrphy_apb_wr(0x541ef,0x0);
+	dwc_ddrphy_apb_wr(0x541f0,0x0);
+	dwc_ddrphy_apb_wr(0x541f1,0x0);
+	dwc_ddrphy_apb_wr(0x541f2,0x0);
+	dwc_ddrphy_apb_wr(0x541f3,0x0);
+	dwc_ddrphy_apb_wr(0x541f4,0x0);
+	dwc_ddrphy_apb_wr(0x541f5,0x0);
+	dwc_ddrphy_apb_wr(0x541f6,0x0);
+	dwc_ddrphy_apb_wr(0x541f7,0x0);
+	dwc_ddrphy_apb_wr(0x541f8,0x0);
+	dwc_ddrphy_apb_wr(0x541f9,0x0);
+	dwc_ddrphy_apb_wr(0x541fa,0x0);
+	dwc_ddrphy_apb_wr(0x541fb,0x0);
+	dwc_ddrphy_apb_wr(0x541fc,0x100);
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0099,0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0099,0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
+
+	wait_ddrphy_training_complete();
+
+	dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+
+	ddr_load_train_code(FW_2D_IMAGE);
+
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0x54000,0x80);/* should be 0x80 in silicon */
+	dwc_ddrphy_apb_wr(0x54001,0x0);
+	dwc_ddrphy_apb_wr(0x54002,0x0);
+	dwc_ddrphy_apb_wr(0x54003,0x960);
+	dwc_ddrphy_apb_wr(0x54004,0x2);
+
+	dwc_ddrphy_apb_wr(0x54005,((PHY_RON<<8)|(PHY_RTT<<0))/*0x2830*/);
+	dwc_ddrphy_apb_wr(0x54006,(0x200|PHYREF_VALUE)/*0x23b*/);
+	dwc_ddrphy_apb_wr(0x54007,0x2000);
+
+	dwc_ddrphy_apb_wr(0x54008,0x303);
+
+	dwc_ddrphy_apb_wr(0x54009,0x200);
+	dwc_ddrphy_apb_wr(0x5400a,0x0);
+	dwc_ddrphy_apb_wr(0x5400b,0x61);/* should be 0x61 in silicon */
+
+	dwc_ddrphy_apb_wr(0x5400c,0xc8); /* 0xc8 indicates stage completion messages showed */
+
+	dwc_ddrphy_apb_wr(0x5400d,0x0);
+	dwc_ddrphy_apb_wr(0x5400e,0x8020);
+	dwc_ddrphy_apb_wr(0x5400f,0x0);
+	dwc_ddrphy_apb_wr(0x54010,0x0);
+	dwc_ddrphy_apb_wr(0x54011,0x0);
+	dwc_ddrphy_apb_wr(0x54012,0x1);
+	dwc_ddrphy_apb_wr(0x54013,0x0);
+	dwc_ddrphy_apb_wr(0x54014,0x0);
+	dwc_ddrphy_apb_wr(0x54015,0x0);
+	dwc_ddrphy_apb_wr(0x54016,0x0);
+	dwc_ddrphy_apb_wr(0x54017,0x0);
+	dwc_ddrphy_apb_wr(0x54018,0x0);
+	dwc_ddrphy_apb_wr(0x54019,0x0);
+	dwc_ddrphy_apb_wr(0x5401a,0x0);
+	dwc_ddrphy_apb_wr(0x5401b,0x0);
+	dwc_ddrphy_apb_wr(0x5401c,0x0);
+	dwc_ddrphy_apb_wr(0x5401d,0x0);
+	dwc_ddrphy_apb_wr(0x5401e,0x0);
+	dwc_ddrphy_apb_wr(0x5401f,0x0);
+	dwc_ddrphy_apb_wr(0x54020,0x0);
+	dwc_ddrphy_apb_wr(0x54021,0x0);
+	dwc_ddrphy_apb_wr(0x54022,0x0);
+	dwc_ddrphy_apb_wr(0x54023,0x0);
+	dwc_ddrphy_apb_wr(0x54024,0x0);
+	dwc_ddrphy_apb_wr(0x54025,0x0);
+	dwc_ddrphy_apb_wr(0x54026,0x0);
+	dwc_ddrphy_apb_wr(0x54027,0x0);
+	dwc_ddrphy_apb_wr(0x54028,0x0);
+	dwc_ddrphy_apb_wr(0x54029,0x0);
+	dwc_ddrphy_apb_wr(0x5402a,0x0);
+	dwc_ddrphy_apb_wr(0x5402b,0x0);
+	dwc_ddrphy_apb_wr(0x5402c,0x0);
+	dwc_ddrphy_apb_wr(0x5402d,0x0);
+	dwc_ddrphy_apb_wr(0x5402e,0x0);
+
+	dwc_ddrphy_apb_wr(0x5402f,0xa30);/* MR0 */
+	dwc_ddrphy_apb_wr(0x54030, ((DDR_RTT<<8)|(DDR_RON<<1)|0x1)/*0x1*/);/* MR1 */
+	dwc_ddrphy_apb_wr(0x54031,0x1018);/* MR2 */
+	dwc_ddrphy_apb_wr(0x54032,0x240);/* MR3 */
+	dwc_ddrphy_apb_wr(0x54033,0xa00);/* MR4 */
+	dwc_ddrphy_apb_wr(0x54034,0x42);/* MR5 */
+	dwc_ddrphy_apb_wr(0x54035,(0x800|MR6_VALUE)/*0x800*/);/* MR6 */
+
+	dwc_ddrphy_apb_wr(0x54036,0x103);
+	dwc_ddrphy_apb_wr(0x54037,0x0);
+	dwc_ddrphy_apb_wr(0x54038,0x0);
+	dwc_ddrphy_apb_wr(0x54039,0x0);
+	dwc_ddrphy_apb_wr(0x5403a,0x0);
+	dwc_ddrphy_apb_wr(0x5403b,0x0);
+	dwc_ddrphy_apb_wr(0x5403c,0x0);
+	dwc_ddrphy_apb_wr(0x5403d,0x0);
+	dwc_ddrphy_apb_wr(0x5403e,0x0);
+	dwc_ddrphy_apb_wr(0x5403f,0x1221);
+	dwc_ddrphy_apb_wr(0x54040,0x0);
+	dwc_ddrphy_apb_wr(0x54041,0x0);
+	dwc_ddrphy_apb_wr(0x54042,0x0);
+	dwc_ddrphy_apb_wr(0x54043,0x0);
+	dwc_ddrphy_apb_wr(0x54044,0x0);
+	dwc_ddrphy_apb_wr(0x54045,0x0);
+	dwc_ddrphy_apb_wr(0x54046,0x0);
+	dwc_ddrphy_apb_wr(0x54047,0x0);
+	dwc_ddrphy_apb_wr(0x54048,0x0);
+	dwc_ddrphy_apb_wr(0x54049,0x0);
+	dwc_ddrphy_apb_wr(0x5404a,0x0);
+	dwc_ddrphy_apb_wr(0x5404b,0x0);
+	dwc_ddrphy_apb_wr(0x5404c,0x0);
+	dwc_ddrphy_apb_wr(0x5404d,0x0);
+	dwc_ddrphy_apb_wr(0x5404e,0x0);
+	dwc_ddrphy_apb_wr(0x5404f,0x0);
+	dwc_ddrphy_apb_wr(0x54050,0x0);
+	dwc_ddrphy_apb_wr(0x54051,0x0);
+	dwc_ddrphy_apb_wr(0x54052,0x0);
+	dwc_ddrphy_apb_wr(0x54053,0x0);
+	dwc_ddrphy_apb_wr(0x54054,0x0);
+	dwc_ddrphy_apb_wr(0x54055,0x0);
+	dwc_ddrphy_apb_wr(0x54056,0x0);
+	dwc_ddrphy_apb_wr(0x54057,0x0);
+	dwc_ddrphy_apb_wr(0x54058,0x0);
+	dwc_ddrphy_apb_wr(0x54059,0x0);
+	dwc_ddrphy_apb_wr(0x5405a,0x0);
+	dwc_ddrphy_apb_wr(0x5405b,0x0);
+	dwc_ddrphy_apb_wr(0x5405c,0x0);
+	dwc_ddrphy_apb_wr(0x5405d,0x0);
+	dwc_ddrphy_apb_wr(0x5405e,0x0);
+	dwc_ddrphy_apb_wr(0x5405f,0x0);
+	dwc_ddrphy_apb_wr(0x54060,0x0);
+	dwc_ddrphy_apb_wr(0x54061,0x0);
+	dwc_ddrphy_apb_wr(0x54062,0x0);
+	dwc_ddrphy_apb_wr(0x54063,0x0);
+	dwc_ddrphy_apb_wr(0x54064,0x0);
+	dwc_ddrphy_apb_wr(0x54065,0x0);
+	dwc_ddrphy_apb_wr(0x54066,0x0);
+	dwc_ddrphy_apb_wr(0x54067,0x0);
+	dwc_ddrphy_apb_wr(0x54068,0x0);
+	dwc_ddrphy_apb_wr(0x54069,0x0);
+	dwc_ddrphy_apb_wr(0x5406a,0x0);
+	dwc_ddrphy_apb_wr(0x5406b,0x0);
+	dwc_ddrphy_apb_wr(0x5406c,0x0);
+	dwc_ddrphy_apb_wr(0x5406d,0x0);
+	dwc_ddrphy_apb_wr(0x5406e,0x0);
+	dwc_ddrphy_apb_wr(0x5406f,0x0);
+	dwc_ddrphy_apb_wr(0x54070,0x0);
+	dwc_ddrphy_apb_wr(0x54071,0x0);
+	dwc_ddrphy_apb_wr(0x54072,0x0);
+	dwc_ddrphy_apb_wr(0x54073,0x0);
+	dwc_ddrphy_apb_wr(0x54074,0x0);
+	dwc_ddrphy_apb_wr(0x54075,0x0);
+	dwc_ddrphy_apb_wr(0x54076,0x0);
+	dwc_ddrphy_apb_wr(0x54077,0x0);
+	dwc_ddrphy_apb_wr(0x54078,0x0);
+	dwc_ddrphy_apb_wr(0x54079,0x0);
+	dwc_ddrphy_apb_wr(0x5407a,0x0);
+	dwc_ddrphy_apb_wr(0x5407b,0x0);
+	dwc_ddrphy_apb_wr(0x5407c,0x0);
+	dwc_ddrphy_apb_wr(0x5407d,0x0);
+	dwc_ddrphy_apb_wr(0x5407e,0x0);
+	dwc_ddrphy_apb_wr(0x5407f,0x0);
+	dwc_ddrphy_apb_wr(0x54080,0x0);
+	dwc_ddrphy_apb_wr(0x54081,0x0);
+	dwc_ddrphy_apb_wr(0x54082,0x0);
+	dwc_ddrphy_apb_wr(0x54083,0x0);
+	dwc_ddrphy_apb_wr(0x54084,0x0);
+	dwc_ddrphy_apb_wr(0x54085,0x0);
+	dwc_ddrphy_apb_wr(0x54086,0x0);
+	dwc_ddrphy_apb_wr(0x54087,0x0);
+	dwc_ddrphy_apb_wr(0x54088,0x0);
+	dwc_ddrphy_apb_wr(0x54089,0x0);
+	dwc_ddrphy_apb_wr(0x5408a,0x0);
+	dwc_ddrphy_apb_wr(0x5408b,0x0);
+	dwc_ddrphy_apb_wr(0x5408c,0x0);
+	dwc_ddrphy_apb_wr(0x5408d,0x0);
+	dwc_ddrphy_apb_wr(0x5408e,0x0);
+	dwc_ddrphy_apb_wr(0x5408f,0x0);
+	dwc_ddrphy_apb_wr(0x54090,0x0);
+	dwc_ddrphy_apb_wr(0x54091,0x0);
+	dwc_ddrphy_apb_wr(0x54092,0x0);
+	dwc_ddrphy_apb_wr(0x54093,0x0);
+	dwc_ddrphy_apb_wr(0x54094,0x0);
+	dwc_ddrphy_apb_wr(0x54095,0x0);
+	dwc_ddrphy_apb_wr(0x54096,0x0);
+	dwc_ddrphy_apb_wr(0x54097,0x0);
+	dwc_ddrphy_apb_wr(0x54098,0x0);
+	dwc_ddrphy_apb_wr(0x54099,0x0);
+	dwc_ddrphy_apb_wr(0x5409a,0x0);
+	dwc_ddrphy_apb_wr(0x5409b,0x0);
+	dwc_ddrphy_apb_wr(0x5409c,0x0);
+	dwc_ddrphy_apb_wr(0x5409d,0x0);
+	dwc_ddrphy_apb_wr(0x5409e,0x0);
+	dwc_ddrphy_apb_wr(0x5409f,0x0);
+	dwc_ddrphy_apb_wr(0x540a0,0x0);
+	dwc_ddrphy_apb_wr(0x540a1,0x0);
+	dwc_ddrphy_apb_wr(0x540a2,0x0);
+	dwc_ddrphy_apb_wr(0x540a3,0x0);
+	dwc_ddrphy_apb_wr(0x540a4,0x0);
+	dwc_ddrphy_apb_wr(0x540a5,0x0);
+	dwc_ddrphy_apb_wr(0x540a6,0x0);
+	dwc_ddrphy_apb_wr(0x540a7,0x0);
+	dwc_ddrphy_apb_wr(0x540a8,0x0);
+	dwc_ddrphy_apb_wr(0x540a9,0x0);
+	dwc_ddrphy_apb_wr(0x540aa,0x0);
+	dwc_ddrphy_apb_wr(0x540ab,0x0);
+	dwc_ddrphy_apb_wr(0x540ac,0x0);
+	dwc_ddrphy_apb_wr(0x540ad,0x0);
+	dwc_ddrphy_apb_wr(0x540ae,0x0);
+	dwc_ddrphy_apb_wr(0x540af,0x0);
+	dwc_ddrphy_apb_wr(0x540b0,0x0);
+	dwc_ddrphy_apb_wr(0x540b1,0x0);
+	dwc_ddrphy_apb_wr(0x540b2,0x0);
+	dwc_ddrphy_apb_wr(0x540b3,0x0);
+	dwc_ddrphy_apb_wr(0x540b4,0x0);
+	dwc_ddrphy_apb_wr(0x540b5,0x0);
+	dwc_ddrphy_apb_wr(0x540b6,0x0);
+	dwc_ddrphy_apb_wr(0x540b7,0x0);
+	dwc_ddrphy_apb_wr(0x540b8,0x0);
+	dwc_ddrphy_apb_wr(0x540b9,0x0);
+	dwc_ddrphy_apb_wr(0x540ba,0x0);
+	dwc_ddrphy_apb_wr(0x540bb,0x0);
+	dwc_ddrphy_apb_wr(0x540bc,0x0);
+	dwc_ddrphy_apb_wr(0x540bd,0x0);
+	dwc_ddrphy_apb_wr(0x540be,0x0);
+	dwc_ddrphy_apb_wr(0x540bf,0x0);
+	dwc_ddrphy_apb_wr(0x540c0,0x0);
+	dwc_ddrphy_apb_wr(0x540c1,0x0);
+	dwc_ddrphy_apb_wr(0x540c2,0x0);
+	dwc_ddrphy_apb_wr(0x540c3,0x0);
+	dwc_ddrphy_apb_wr(0x540c4,0x0);
+	dwc_ddrphy_apb_wr(0x540c5,0x0);
+	dwc_ddrphy_apb_wr(0x540c6,0x0);
+	dwc_ddrphy_apb_wr(0x540c7,0x0);
+	dwc_ddrphy_apb_wr(0x540c8,0x0);
+	dwc_ddrphy_apb_wr(0x540c9,0x0);
+	dwc_ddrphy_apb_wr(0x540ca,0x0);
+	dwc_ddrphy_apb_wr(0x540cb,0x0);
+	dwc_ddrphy_apb_wr(0x540cc,0x0);
+	dwc_ddrphy_apb_wr(0x540cd,0x0);
+	dwc_ddrphy_apb_wr(0x540ce,0x0);
+	dwc_ddrphy_apb_wr(0x540cf,0x0);
+	dwc_ddrphy_apb_wr(0x540d0,0x0);
+	dwc_ddrphy_apb_wr(0x540d1,0x0);
+	dwc_ddrphy_apb_wr(0x540d2,0x0);
+	dwc_ddrphy_apb_wr(0x540d3,0x0);
+	dwc_ddrphy_apb_wr(0x540d4,0x0);
+	dwc_ddrphy_apb_wr(0x540d5,0x0);
+	dwc_ddrphy_apb_wr(0x540d6,0x0);
+	dwc_ddrphy_apb_wr(0x540d7,0x0);
+	dwc_ddrphy_apb_wr(0x540d8,0x0);
+	dwc_ddrphy_apb_wr(0x540d9,0x0);
+	dwc_ddrphy_apb_wr(0x540da,0x0);
+	dwc_ddrphy_apb_wr(0x540db,0x0);
+	dwc_ddrphy_apb_wr(0x540dc,0x0);
+	dwc_ddrphy_apb_wr(0x540dd,0x0);
+	dwc_ddrphy_apb_wr(0x540de,0x0);
+	dwc_ddrphy_apb_wr(0x540df,0x0);
+	dwc_ddrphy_apb_wr(0x540e0,0x0);
+	dwc_ddrphy_apb_wr(0x540e1,0x0);
+	dwc_ddrphy_apb_wr(0x540e2,0x0);
+	dwc_ddrphy_apb_wr(0x540e3,0x0);
+	dwc_ddrphy_apb_wr(0x540e4,0x0);
+	dwc_ddrphy_apb_wr(0x540e5,0x0);
+	dwc_ddrphy_apb_wr(0x540e6,0x0);
+	dwc_ddrphy_apb_wr(0x540e7,0x0);
+	dwc_ddrphy_apb_wr(0x540e8,0x0);
+	dwc_ddrphy_apb_wr(0x540e9,0x0);
+	dwc_ddrphy_apb_wr(0x540ea,0x0);
+	dwc_ddrphy_apb_wr(0x540eb,0x0);
+	dwc_ddrphy_apb_wr(0x540ec,0x0);
+	dwc_ddrphy_apb_wr(0x540ed,0x0);
+	dwc_ddrphy_apb_wr(0x540ee,0x0);
+	dwc_ddrphy_apb_wr(0x540ef,0x0);
+	dwc_ddrphy_apb_wr(0x540f0,0x0);
+	dwc_ddrphy_apb_wr(0x540f1,0x0);
+	dwc_ddrphy_apb_wr(0x540f2,0x0);
+	dwc_ddrphy_apb_wr(0x540f3,0x0);
+	dwc_ddrphy_apb_wr(0x540f4,0x0);
+	dwc_ddrphy_apb_wr(0x540f5,0x0);
+	dwc_ddrphy_apb_wr(0x540f6,0x0);
+	dwc_ddrphy_apb_wr(0x540f7,0x0);
+	dwc_ddrphy_apb_wr(0x540f8,0x0);
+	dwc_ddrphy_apb_wr(0x540f9,0x0);
+	dwc_ddrphy_apb_wr(0x540fa,0x0);
+	dwc_ddrphy_apb_wr(0x540fb,0x0);
+	dwc_ddrphy_apb_wr(0x540fc,0x0);
+	dwc_ddrphy_apb_wr(0x540fd,0x0);
+	dwc_ddrphy_apb_wr(0x540fe,0x0);
+	dwc_ddrphy_apb_wr(0x540ff,0x0);
+	dwc_ddrphy_apb_wr(0x54100,0x0);
+	dwc_ddrphy_apb_wr(0x54101,0x0);
+	dwc_ddrphy_apb_wr(0x54102,0x0);
+	dwc_ddrphy_apb_wr(0x54103,0x0);
+	dwc_ddrphy_apb_wr(0x54104,0x0);
+	dwc_ddrphy_apb_wr(0x54105,0x0);
+	dwc_ddrphy_apb_wr(0x54106,0x0);
+	dwc_ddrphy_apb_wr(0x54107,0x0);
+	dwc_ddrphy_apb_wr(0x54108,0x0);
+	dwc_ddrphy_apb_wr(0x54109,0x0);
+	dwc_ddrphy_apb_wr(0x5410a,0x0);
+	dwc_ddrphy_apb_wr(0x5410b,0x0);
+	dwc_ddrphy_apb_wr(0x5410c,0x0);
+	dwc_ddrphy_apb_wr(0x5410d,0x0);
+	dwc_ddrphy_apb_wr(0x5410e,0x0);
+	dwc_ddrphy_apb_wr(0x5410f,0x0);
+	dwc_ddrphy_apb_wr(0x54110,0x0);
+	dwc_ddrphy_apb_wr(0x54111,0x0);
+	dwc_ddrphy_apb_wr(0x54112,0x0);
+	dwc_ddrphy_apb_wr(0x54113,0x0);
+	dwc_ddrphy_apb_wr(0x54114,0x0);
+	dwc_ddrphy_apb_wr(0x54115,0x0);
+	dwc_ddrphy_apb_wr(0x54116,0x0);
+	dwc_ddrphy_apb_wr(0x54117,0x0);
+	dwc_ddrphy_apb_wr(0x54118,0x0);
+	dwc_ddrphy_apb_wr(0x54119,0x0);
+	dwc_ddrphy_apb_wr(0x5411a,0x0);
+	dwc_ddrphy_apb_wr(0x5411b,0x0);
+	dwc_ddrphy_apb_wr(0x5411c,0x0);
+	dwc_ddrphy_apb_wr(0x5411d,0x0);
+	dwc_ddrphy_apb_wr(0x5411e,0x0);
+	dwc_ddrphy_apb_wr(0x5411f,0x0);
+	dwc_ddrphy_apb_wr(0x54120,0x0);
+	dwc_ddrphy_apb_wr(0x54121,0x0);
+	dwc_ddrphy_apb_wr(0x54122,0x0);
+	dwc_ddrphy_apb_wr(0x54123,0x0);
+	dwc_ddrphy_apb_wr(0x54124,0x0);
+	dwc_ddrphy_apb_wr(0x54125,0x0);
+	dwc_ddrphy_apb_wr(0x54126,0x0);
+	dwc_ddrphy_apb_wr(0x54127,0x0);
+	dwc_ddrphy_apb_wr(0x54128,0x0);
+	dwc_ddrphy_apb_wr(0x54129,0x0);
+	dwc_ddrphy_apb_wr(0x5412a,0x0);
+	dwc_ddrphy_apb_wr(0x5412b,0x0);
+	dwc_ddrphy_apb_wr(0x5412c,0x0);
+	dwc_ddrphy_apb_wr(0x5412d,0x0);
+	dwc_ddrphy_apb_wr(0x5412e,0x0);
+	dwc_ddrphy_apb_wr(0x5412f,0x0);
+	dwc_ddrphy_apb_wr(0x54130,0x0);
+	dwc_ddrphy_apb_wr(0x54131,0x0);
+	dwc_ddrphy_apb_wr(0x54132,0x0);
+	dwc_ddrphy_apb_wr(0x54133,0x0);
+	dwc_ddrphy_apb_wr(0x54134,0x0);
+	dwc_ddrphy_apb_wr(0x54135,0x0);
+	dwc_ddrphy_apb_wr(0x54136,0x0);
+	dwc_ddrphy_apb_wr(0x54137,0x0);
+	dwc_ddrphy_apb_wr(0x54138,0x0);
+	dwc_ddrphy_apb_wr(0x54139,0x0);
+	dwc_ddrphy_apb_wr(0x5413a,0x0);
+	dwc_ddrphy_apb_wr(0x5413b,0x0);
+	dwc_ddrphy_apb_wr(0x5413c,0x0);
+	dwc_ddrphy_apb_wr(0x5413d,0x0);
+	dwc_ddrphy_apb_wr(0x5413e,0x0);
+	dwc_ddrphy_apb_wr(0x5413f,0x0);
+	dwc_ddrphy_apb_wr(0x54140,0x0);
+	dwc_ddrphy_apb_wr(0x54141,0x0);
+	dwc_ddrphy_apb_wr(0x54142,0x0);
+	dwc_ddrphy_apb_wr(0x54143,0x0);
+	dwc_ddrphy_apb_wr(0x54144,0x0);
+	dwc_ddrphy_apb_wr(0x54145,0x0);
+	dwc_ddrphy_apb_wr(0x54146,0x0);
+	dwc_ddrphy_apb_wr(0x54147,0x0);
+	dwc_ddrphy_apb_wr(0x54148,0x0);
+	dwc_ddrphy_apb_wr(0x54149,0x0);
+	dwc_ddrphy_apb_wr(0x5414a,0x0);
+	dwc_ddrphy_apb_wr(0x5414b,0x0);
+	dwc_ddrphy_apb_wr(0x5414c,0x0);
+	dwc_ddrphy_apb_wr(0x5414d,0x0);
+	dwc_ddrphy_apb_wr(0x5414e,0x0);
+	dwc_ddrphy_apb_wr(0x5414f,0x0);
+	dwc_ddrphy_apb_wr(0x54150,0x0);
+	dwc_ddrphy_apb_wr(0x54151,0x0);
+	dwc_ddrphy_apb_wr(0x54152,0x0);
+	dwc_ddrphy_apb_wr(0x54153,0x0);
+	dwc_ddrphy_apb_wr(0x54154,0x0);
+	dwc_ddrphy_apb_wr(0x54155,0x0);
+	dwc_ddrphy_apb_wr(0x54156,0x0);
+	dwc_ddrphy_apb_wr(0x54157,0x0);
+	dwc_ddrphy_apb_wr(0x54158,0x0);
+	dwc_ddrphy_apb_wr(0x54159,0x0);
+	dwc_ddrphy_apb_wr(0x5415a,0x0);
+	dwc_ddrphy_apb_wr(0x5415b,0x0);
+	dwc_ddrphy_apb_wr(0x5415c,0x0);
+	dwc_ddrphy_apb_wr(0x5415d,0x0);
+	dwc_ddrphy_apb_wr(0x5415e,0x0);
+	dwc_ddrphy_apb_wr(0x5415f,0x0);
+	dwc_ddrphy_apb_wr(0x54160,0x0);
+	dwc_ddrphy_apb_wr(0x54161,0x0);
+	dwc_ddrphy_apb_wr(0x54162,0x0);
+	dwc_ddrphy_apb_wr(0x54163,0x0);
+	dwc_ddrphy_apb_wr(0x54164,0x0);
+	dwc_ddrphy_apb_wr(0x54165,0x0);
+	dwc_ddrphy_apb_wr(0x54166,0x0);
+	dwc_ddrphy_apb_wr(0x54167,0x0);
+	dwc_ddrphy_apb_wr(0x54168,0x0);
+	dwc_ddrphy_apb_wr(0x54169,0x0);
+	dwc_ddrphy_apb_wr(0x5416a,0x0);
+	dwc_ddrphy_apb_wr(0x5416b,0x0);
+	dwc_ddrphy_apb_wr(0x5416c,0x0);
+	dwc_ddrphy_apb_wr(0x5416d,0x0);
+	dwc_ddrphy_apb_wr(0x5416e,0x0);
+	dwc_ddrphy_apb_wr(0x5416f,0x0);
+	dwc_ddrphy_apb_wr(0x54170,0x0);
+	dwc_ddrphy_apb_wr(0x54171,0x0);
+	dwc_ddrphy_apb_wr(0x54172,0x0);
+	dwc_ddrphy_apb_wr(0x54173,0x0);
+	dwc_ddrphy_apb_wr(0x54174,0x0);
+	dwc_ddrphy_apb_wr(0x54175,0x0);
+	dwc_ddrphy_apb_wr(0x54176,0x0);
+	dwc_ddrphy_apb_wr(0x54177,0x0);
+	dwc_ddrphy_apb_wr(0x54178,0x0);
+	dwc_ddrphy_apb_wr(0x54179,0x0);
+	dwc_ddrphy_apb_wr(0x5417a,0x0);
+	dwc_ddrphy_apb_wr(0x5417b,0x0);
+	dwc_ddrphy_apb_wr(0x5417c,0x0);
+	dwc_ddrphy_apb_wr(0x5417d,0x0);
+	dwc_ddrphy_apb_wr(0x5417e,0x0);
+	dwc_ddrphy_apb_wr(0x5417f,0x0);
+	dwc_ddrphy_apb_wr(0x54180,0x0);
+	dwc_ddrphy_apb_wr(0x54181,0x0);
+	dwc_ddrphy_apb_wr(0x54182,0x0);
+	dwc_ddrphy_apb_wr(0x54183,0x0);
+	dwc_ddrphy_apb_wr(0x54184,0x0);
+	dwc_ddrphy_apb_wr(0x54185,0x0);
+	dwc_ddrphy_apb_wr(0x54186,0x0);
+	dwc_ddrphy_apb_wr(0x54187,0x0);
+	dwc_ddrphy_apb_wr(0x54188,0x0);
+	dwc_ddrphy_apb_wr(0x54189,0x0);
+	dwc_ddrphy_apb_wr(0x5418a,0x0);
+	dwc_ddrphy_apb_wr(0x5418b,0x0);
+	dwc_ddrphy_apb_wr(0x5418c,0x0);
+	dwc_ddrphy_apb_wr(0x5418d,0x0);
+	dwc_ddrphy_apb_wr(0x5418e,0x0);
+	dwc_ddrphy_apb_wr(0x5418f,0x0);
+	dwc_ddrphy_apb_wr(0x54190,0x0);
+	dwc_ddrphy_apb_wr(0x54191,0x0);
+	dwc_ddrphy_apb_wr(0x54192,0x0);
+	dwc_ddrphy_apb_wr(0x54193,0x0);
+	dwc_ddrphy_apb_wr(0x54194,0x0);
+	dwc_ddrphy_apb_wr(0x54195,0x0);
+	dwc_ddrphy_apb_wr(0x54196,0x0);
+	dwc_ddrphy_apb_wr(0x54197,0x0);
+	dwc_ddrphy_apb_wr(0x54198,0x0);
+	dwc_ddrphy_apb_wr(0x54199,0x0);
+	dwc_ddrphy_apb_wr(0x5419a,0x0);
+	dwc_ddrphy_apb_wr(0x5419b,0x0);
+	dwc_ddrphy_apb_wr(0x5419c,0x0);
+	dwc_ddrphy_apb_wr(0x5419d,0x0);
+	dwc_ddrphy_apb_wr(0x5419e,0x0);
+	dwc_ddrphy_apb_wr(0x5419f,0x0);
+	dwc_ddrphy_apb_wr(0x541a0,0x0);
+	dwc_ddrphy_apb_wr(0x541a1,0x0);
+	dwc_ddrphy_apb_wr(0x541a2,0x0);
+	dwc_ddrphy_apb_wr(0x541a3,0x0);
+	dwc_ddrphy_apb_wr(0x541a4,0x0);
+	dwc_ddrphy_apb_wr(0x541a5,0x0);
+	dwc_ddrphy_apb_wr(0x541a6,0x0);
+	dwc_ddrphy_apb_wr(0x541a7,0x0);
+	dwc_ddrphy_apb_wr(0x541a8,0x0);
+	dwc_ddrphy_apb_wr(0x541a9,0x0);
+	dwc_ddrphy_apb_wr(0x541aa,0x0);
+	dwc_ddrphy_apb_wr(0x541ab,0x0);
+	dwc_ddrphy_apb_wr(0x541ac,0x0);
+	dwc_ddrphy_apb_wr(0x541ad,0x0);
+	dwc_ddrphy_apb_wr(0x541ae,0x0);
+	dwc_ddrphy_apb_wr(0x541af,0x0);
+	dwc_ddrphy_apb_wr(0x541b0,0x0);
+	dwc_ddrphy_apb_wr(0x541b1,0x0);
+	dwc_ddrphy_apb_wr(0x541b2,0x0);
+	dwc_ddrphy_apb_wr(0x541b3,0x0);
+	dwc_ddrphy_apb_wr(0x541b4,0x0);
+	dwc_ddrphy_apb_wr(0x541b5,0x0);
+	dwc_ddrphy_apb_wr(0x541b6,0x0);
+	dwc_ddrphy_apb_wr(0x541b7,0x0);
+	dwc_ddrphy_apb_wr(0x541b8,0x0);
+	dwc_ddrphy_apb_wr(0x541b9,0x0);
+	dwc_ddrphy_apb_wr(0x541ba,0x0);
+	dwc_ddrphy_apb_wr(0x541bb,0x0);
+	dwc_ddrphy_apb_wr(0x541bc,0x0);
+	dwc_ddrphy_apb_wr(0x541bd,0x0);
+	dwc_ddrphy_apb_wr(0x541be,0x0);
+	dwc_ddrphy_apb_wr(0x541bf,0x0);
+	dwc_ddrphy_apb_wr(0x541c0,0x0);
+	dwc_ddrphy_apb_wr(0x541c1,0x0);
+	dwc_ddrphy_apb_wr(0x541c2,0x0);
+	dwc_ddrphy_apb_wr(0x541c3,0x0);
+	dwc_ddrphy_apb_wr(0x541c4,0x0);
+	dwc_ddrphy_apb_wr(0x541c5,0x0);
+	dwc_ddrphy_apb_wr(0x541c6,0x0);
+	dwc_ddrphy_apb_wr(0x541c7,0x0);
+	dwc_ddrphy_apb_wr(0x541c8,0x0);
+	dwc_ddrphy_apb_wr(0x541c9,0x0);
+	dwc_ddrphy_apb_wr(0x541ca,0x0);
+	dwc_ddrphy_apb_wr(0x541cb,0x0);
+	dwc_ddrphy_apb_wr(0x541cc,0x0);
+	dwc_ddrphy_apb_wr(0x541cd,0x0);
+	dwc_ddrphy_apb_wr(0x541ce,0x0);
+	dwc_ddrphy_apb_wr(0x541cf,0x0);
+	dwc_ddrphy_apb_wr(0x541d0,0x0);
+	dwc_ddrphy_apb_wr(0x541d1,0x0);
+	dwc_ddrphy_apb_wr(0x541d2,0x0);
+	dwc_ddrphy_apb_wr(0x541d3,0x0);
+	dwc_ddrphy_apb_wr(0x541d4,0x0);
+	dwc_ddrphy_apb_wr(0x541d5,0x0);
+	dwc_ddrphy_apb_wr(0x541d6,0x0);
+	dwc_ddrphy_apb_wr(0x541d7,0x0);
+	dwc_ddrphy_apb_wr(0x541d8,0x0);
+	dwc_ddrphy_apb_wr(0x541d9,0x0);
+	dwc_ddrphy_apb_wr(0x541da,0x0);
+	dwc_ddrphy_apb_wr(0x541db,0x0);
+	dwc_ddrphy_apb_wr(0x541dc,0x0);
+	dwc_ddrphy_apb_wr(0x541dd,0x0);
+	dwc_ddrphy_apb_wr(0x541de,0x0);
+	dwc_ddrphy_apb_wr(0x541df,0x0);
+	dwc_ddrphy_apb_wr(0x541e0,0x0);
+	dwc_ddrphy_apb_wr(0x541e1,0x0);
+	dwc_ddrphy_apb_wr(0x541e2,0x0);
+	dwc_ddrphy_apb_wr(0x541e3,0x0);
+	dwc_ddrphy_apb_wr(0x541e4,0x0);
+	dwc_ddrphy_apb_wr(0x541e5,0x0);
+	dwc_ddrphy_apb_wr(0x541e6,0x0);
+	dwc_ddrphy_apb_wr(0x541e7,0x0);
+	dwc_ddrphy_apb_wr(0x541e8,0x0);
+	dwc_ddrphy_apb_wr(0x541e9,0x0);
+	dwc_ddrphy_apb_wr(0x541ea,0x0);
+	dwc_ddrphy_apb_wr(0x541eb,0x0);
+	dwc_ddrphy_apb_wr(0x541ec,0x0);
+	dwc_ddrphy_apb_wr(0x541ed,0x0);
+	dwc_ddrphy_apb_wr(0x541ee,0x0);
+	dwc_ddrphy_apb_wr(0x541ef,0x0);
+	dwc_ddrphy_apb_wr(0x541f0,0x0);
+	dwc_ddrphy_apb_wr(0x541f1,0x0);
+	dwc_ddrphy_apb_wr(0x541f2,0x0);
+	dwc_ddrphy_apb_wr(0x541f3,0x0);
+	dwc_ddrphy_apb_wr(0x541f4,0x0);
+	dwc_ddrphy_apb_wr(0x541f5,0x0);
+	dwc_ddrphy_apb_wr(0x541f6,0x0);
+	dwc_ddrphy_apb_wr(0x541f7,0x0);
+	dwc_ddrphy_apb_wr(0x541f8,0x0);
+	dwc_ddrphy_apb_wr(0x541f9,0x0);
+	dwc_ddrphy_apb_wr(0x541fa,0x0);
+	dwc_ddrphy_apb_wr(0x541fb,0x0);
+	dwc_ddrphy_apb_wr(0x541fc,0x100);
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0099,0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0099,0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */
+
+	wait_ddrphy_training_complete();
+
+	dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0x90000,0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
+	dwc_ddrphy_apb_wr(0x90001,0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
+	dwc_ddrphy_apb_wr(0x90002,0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
+	dwc_ddrphy_apb_wr(0x90003,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
+	dwc_ddrphy_apb_wr(0x90004,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
+	dwc_ddrphy_apb_wr(0x90005,0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
+	dwc_ddrphy_apb_wr(0x90029,0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
+	dwc_ddrphy_apb_wr(0x9002a,0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
+	dwc_ddrphy_apb_wr(0x9002b,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
+	dwc_ddrphy_apb_wr(0x9002c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
+	dwc_ddrphy_apb_wr(0x9002d,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
+	dwc_ddrphy_apb_wr(0x9002e,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
+	dwc_ddrphy_apb_wr(0x9002f,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
+	dwc_ddrphy_apb_wr(0x90030,0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
+	dwc_ddrphy_apb_wr(0x90031,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
+	dwc_ddrphy_apb_wr(0x90032,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
+	dwc_ddrphy_apb_wr(0x90033,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
+	dwc_ddrphy_apb_wr(0x90034,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
+	dwc_ddrphy_apb_wr(0x90035,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
+	dwc_ddrphy_apb_wr(0x90036,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
+	dwc_ddrphy_apb_wr(0x90037,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
+	dwc_ddrphy_apb_wr(0x90038,0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
+	dwc_ddrphy_apb_wr(0x90039,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
+	dwc_ddrphy_apb_wr(0x9003a,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
+	dwc_ddrphy_apb_wr(0x9003b,0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
+	dwc_ddrphy_apb_wr(0x9003c,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
+	dwc_ddrphy_apb_wr(0x9003d,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
+	dwc_ddrphy_apb_wr(0x9003e,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
+	dwc_ddrphy_apb_wr(0x9003f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
+	dwc_ddrphy_apb_wr(0x90040,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
+	dwc_ddrphy_apb_wr(0x90041,0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
+	dwc_ddrphy_apb_wr(0x90042,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
+	dwc_ddrphy_apb_wr(0x90043,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
+	dwc_ddrphy_apb_wr(0x90044,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
+	dwc_ddrphy_apb_wr(0x90045,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
+	dwc_ddrphy_apb_wr(0x90046,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
+	dwc_ddrphy_apb_wr(0x90047,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
+	dwc_ddrphy_apb_wr(0x90048,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
+	dwc_ddrphy_apb_wr(0x90049,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
+	dwc_ddrphy_apb_wr(0x9004a,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
+	dwc_ddrphy_apb_wr(0x9004b,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
+	dwc_ddrphy_apb_wr(0x9004c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
+	dwc_ddrphy_apb_wr(0x9004d,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
+	dwc_ddrphy_apb_wr(0x9004e,0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
+	dwc_ddrphy_apb_wr(0x9004f,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
+	dwc_ddrphy_apb_wr(0x90050,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
+	dwc_ddrphy_apb_wr(0x90051,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
+	dwc_ddrphy_apb_wr(0x90052,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
+	dwc_ddrphy_apb_wr(0x90053,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
+	dwc_ddrphy_apb_wr(0x90054,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
+	dwc_ddrphy_apb_wr(0x90055,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
+	dwc_ddrphy_apb_wr(0x90056,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
+	dwc_ddrphy_apb_wr(0x90057,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
+	dwc_ddrphy_apb_wr(0x90058,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
+	dwc_ddrphy_apb_wr(0x90059,0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
+	dwc_ddrphy_apb_wr(0x9005a,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
+	dwc_ddrphy_apb_wr(0x9005b,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
+	dwc_ddrphy_apb_wr(0x9005c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
+	dwc_ddrphy_apb_wr(0x9005d,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
+	dwc_ddrphy_apb_wr(0x9005e,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
+	dwc_ddrphy_apb_wr(0x9005f,0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
+	dwc_ddrphy_apb_wr(0x90060,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
+	dwc_ddrphy_apb_wr(0x90061,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
+	dwc_ddrphy_apb_wr(0x90062,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
+	dwc_ddrphy_apb_wr(0x90063,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
+	dwc_ddrphy_apb_wr(0x90064,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
+	dwc_ddrphy_apb_wr(0x90065,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
+	dwc_ddrphy_apb_wr(0x90066,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
+	dwc_ddrphy_apb_wr(0x90067,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
+	dwc_ddrphy_apb_wr(0x90068,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
+	dwc_ddrphy_apb_wr(0x90069,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
+	dwc_ddrphy_apb_wr(0x9006a,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
+	dwc_ddrphy_apb_wr(0x9006b,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
+	dwc_ddrphy_apb_wr(0x9006c,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
+	dwc_ddrphy_apb_wr(0x9006d,0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
+	dwc_ddrphy_apb_wr(0x9006e,0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
+	dwc_ddrphy_apb_wr(0x9006f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
+	dwc_ddrphy_apb_wr(0x90070,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
+	dwc_ddrphy_apb_wr(0x90071,0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
+	dwc_ddrphy_apb_wr(0x90072,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
+	dwc_ddrphy_apb_wr(0x90073,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
+	dwc_ddrphy_apb_wr(0x90074,0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
+	dwc_ddrphy_apb_wr(0x90075,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
+	dwc_ddrphy_apb_wr(0x90076,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
+	dwc_ddrphy_apb_wr(0x90077,0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
+	dwc_ddrphy_apb_wr(0x90078,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
+	dwc_ddrphy_apb_wr(0x90079,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
+	dwc_ddrphy_apb_wr(0x9007a,0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
+	dwc_ddrphy_apb_wr(0x9007b,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
+	dwc_ddrphy_apb_wr(0x9007c,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
+	dwc_ddrphy_apb_wr(0x9007d,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
+	dwc_ddrphy_apb_wr(0x9007e,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
+	dwc_ddrphy_apb_wr(0x9007f,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
+	dwc_ddrphy_apb_wr(0x90080,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
+	dwc_ddrphy_apb_wr(0x90081,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
+	dwc_ddrphy_apb_wr(0x90082,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
+	dwc_ddrphy_apb_wr(0x90083,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
+	dwc_ddrphy_apb_wr(0x90084,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
+	dwc_ddrphy_apb_wr(0x90085,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
+	dwc_ddrphy_apb_wr(0x90086,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
+	dwc_ddrphy_apb_wr(0x90087,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
+	dwc_ddrphy_apb_wr(0x90088,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
+	dwc_ddrphy_apb_wr(0x90089,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
+	dwc_ddrphy_apb_wr(0x9008a,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
+	dwc_ddrphy_apb_wr(0x9008b,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
+	dwc_ddrphy_apb_wr(0x9008c,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
+	dwc_ddrphy_apb_wr(0x9008d,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
+	dwc_ddrphy_apb_wr(0x9008e,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
+	dwc_ddrphy_apb_wr(0x9008f,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
+	dwc_ddrphy_apb_wr(0x90090,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
+	dwc_ddrphy_apb_wr(0x90091,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
+	dwc_ddrphy_apb_wr(0x90092,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
+	dwc_ddrphy_apb_wr(0x90093,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
+	dwc_ddrphy_apb_wr(0x90094,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
+	dwc_ddrphy_apb_wr(0x90095,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
+	dwc_ddrphy_apb_wr(0x90096,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
+	dwc_ddrphy_apb_wr(0x90097,0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
+	dwc_ddrphy_apb_wr(0x90098,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
+	dwc_ddrphy_apb_wr(0x90099,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
+	dwc_ddrphy_apb_wr(0x9009a,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
+	dwc_ddrphy_apb_wr(0x9009b,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
+	dwc_ddrphy_apb_wr(0x9009c,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
+	dwc_ddrphy_apb_wr(0x9009d,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
+	dwc_ddrphy_apb_wr(0x9009e,0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
+	dwc_ddrphy_apb_wr(0x9009f,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
+	dwc_ddrphy_apb_wr(0x900a0,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
+	dwc_ddrphy_apb_wr(0x900a1,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
+	dwc_ddrphy_apb_wr(0x900a2,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
+	dwc_ddrphy_apb_wr(0x900a3,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
+	dwc_ddrphy_apb_wr(0x900a4,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
+	dwc_ddrphy_apb_wr(0x900a5,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
+	dwc_ddrphy_apb_wr(0x900a6,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
+	dwc_ddrphy_apb_wr(0x900a7,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
+	dwc_ddrphy_apb_wr(0x900a8,0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
+	dwc_ddrphy_apb_wr(0x900a9,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
+	dwc_ddrphy_apb_wr(0x900aa,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
+	dwc_ddrphy_apb_wr(0x900ab,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
+	dwc_ddrphy_apb_wr(0x900ac,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
+	dwc_ddrphy_apb_wr(0x900ad,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
+	dwc_ddrphy_apb_wr(0x900ae,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
+	dwc_ddrphy_apb_wr(0x900af,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
+	dwc_ddrphy_apb_wr(0x900b0,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
+	dwc_ddrphy_apb_wr(0x900b1,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
+	dwc_ddrphy_apb_wr(0x900b2,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
+	dwc_ddrphy_apb_wr(0x900b3,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
+	dwc_ddrphy_apb_wr(0x900b4,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
+	dwc_ddrphy_apb_wr(0x900b5,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
+	dwc_ddrphy_apb_wr(0x900b6,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
+	dwc_ddrphy_apb_wr(0x900b7,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
+	dwc_ddrphy_apb_wr(0x900b8,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
+	dwc_ddrphy_apb_wr(0x900b9,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
+	dwc_ddrphy_apb_wr(0x900ba,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
+	dwc_ddrphy_apb_wr(0x900bb,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
+	dwc_ddrphy_apb_wr(0x900bc,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
+	dwc_ddrphy_apb_wr(0x900bd,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
+	dwc_ddrphy_apb_wr(0x900be,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
+	dwc_ddrphy_apb_wr(0x900bf,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
+	dwc_ddrphy_apb_wr(0x900c0,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
+	dwc_ddrphy_apb_wr(0x900c1,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
+	dwc_ddrphy_apb_wr(0x900c2,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
+	dwc_ddrphy_apb_wr(0x900c3,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
+	dwc_ddrphy_apb_wr(0x900c4,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
+	dwc_ddrphy_apb_wr(0x900c5,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
+	dwc_ddrphy_apb_wr(0x900c6,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
+	dwc_ddrphy_apb_wr(0x900c7,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
+	dwc_ddrphy_apb_wr(0x900c8,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
+	dwc_ddrphy_apb_wr(0x900c9,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
+	dwc_ddrphy_apb_wr(0x900ca,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
+	dwc_ddrphy_apb_wr(0x900cb,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
+	dwc_ddrphy_apb_wr(0x900cc,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
+	dwc_ddrphy_apb_wr(0x900cd,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
+	dwc_ddrphy_apb_wr(0x90006,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
+	dwc_ddrphy_apb_wr(0x90007,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
+	dwc_ddrphy_apb_wr(0x90008,0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
+	dwc_ddrphy_apb_wr(0x90009,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
+	dwc_ddrphy_apb_wr(0x9000a,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
+	dwc_ddrphy_apb_wr(0x9000b,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
+	dwc_ddrphy_apb_wr(0xd00e7,0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */
+	dwc_ddrphy_apb_wr(0x90017,0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */
+	dwc_ddrphy_apb_wr(0x90026,0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */
+	dwc_ddrphy_apb_wr(0x9000c,0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
+	dwc_ddrphy_apb_wr(0x9000d,0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
+	dwc_ddrphy_apb_wr(0x9000e,0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
+	dwc_ddrphy_apb_wr(0x9000f,0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
+	dwc_ddrphy_apb_wr(0x90010,0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
+	dwc_ddrphy_apb_wr(0x90011,0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
+	dwc_ddrphy_apb_wr(0x90012,0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
+	dwc_ddrphy_apb_wr(0x90013,0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
+	dwc_ddrphy_apb_wr(0xc0080,0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+}
diff --git a/board/freescale/imx8mq_val/ddr/helper.c b/board/freescale/imx8mq_val/ddr/helper.c
new file mode 100644
index 00000000000..b9a9bd24635
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/helper.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/sections.h>
+
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_LEN 32768
+#define DMEM_LEN 16384
+#define IMEM_2D_OFFSET 	49152
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+/* We need PHY iMEM PHY is 32KB padded */
+void ddr_load_train_code(enum fw_type type)
+{
+	u32 tmp32, i;
+	u32 error = 0;
+	unsigned long pr_to32, pr_from32;
+	unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+	unsigned long imem_start = (unsigned long)&_end + fw_offset;
+	unsigned long dmem_start = imem_start + IMEM_LEN;
+
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for(i = 0x0; i < IMEM_LEN; ){
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for(i = 0x0; i < DMEM_LEN;){
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	printf("check ddr_imem code\n");
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for(i = 0x0; i < IMEM_LEN;){
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+
+		if(tmp32 != readl(pr_from32)){
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+	if(error){
+		printf("check ddr_imem code fail=%d\n",error);
+	}else{
+		printf("check ddr_imem code pass\n");
+	}
+
+	printf("check ddr_dmem code\n");
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for(i = 0x0; i < DMEM_LEN;){
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+		if(tmp32 != readl(pr_from32)){
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+
+	if(error){
+		printf("check ddr_dmem code fail=%d",error);
+	}else{
+		printf("check ddr_dmem code pass\n");
+	}
+}
diff --git a/board/freescale/imx8mq_val/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mq_val/ddr/wait_ddrphy_training_complete.c
new file mode 100644
index 00000000000..e44072280ee
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/wait_ddrphy_training_complete.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+static inline void poll_pmu_message_ready(void)
+{
+	unsigned int reg;
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+	} while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_recieve(void)
+{
+	unsigned int reg;
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+	} while (!(reg & 0x1));
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+	unsigned int reg;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+	ack_pmu_message_recieve();
+
+	return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+	unsigned int reg, reg2;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+	reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
+
+	reg2 = (reg2 << 16) | reg;
+
+	ack_pmu_message_recieve();
+
+	return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+	ddr_printf("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+	unsigned int string_index, arg __maybe_unused;
+	int i = 0;
+
+	string_index = get_stream_message();
+	ddr_printf("	PMU String index = 0x%08x\n", string_index);
+	while (i < (string_index & 0xffff)){
+		arg = get_stream_message();
+		ddr_printf("	arg[%d] = 0x%08x\n", i, arg);
+		i++;
+	}
+
+	ddr_printf("\n");
+}
+
+int wait_ddrphy_training_complete(void)
+{
+	unsigned int mail;
+	while (1) {
+		mail = get_mail();
+		decode_major_message(mail);
+		if (mail == 0x08) {
+			decode_streaming_message();
+		} else if (mail == 0x07) {
+			printf("Training PASS\n");
+			return 0;
+		} else if (mail == 0xff) {
+			printf("Training FAILED\n");
+			return -1;
+		}
+	}
+}
diff --git a/board/freescale/imx8mq_val/imx8mq_val.c b/board/freescale/imx8mq_val/imx8mq_val.c
new file mode 100644
index 00000000000..afda2f926ca
--- /dev/null
+++ b/board/freescale/imx8mq_val/imx8mq_val.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2019 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NAND_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_QSPI
+int board_qspi_init(void)
+{
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+#ifdef CONFIG_SPL_BUILD
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+	IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+#endif
+
+static void setup_gpmi_nand(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+#endif
+
+	init_nand_clk();
+}
+#endif
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand(); /* SPL will call the board_early_init_f */
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+	/*
+	* GPR1 bit 13:
+	* 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also;
+	* 0:enet1 rmii clock comes from external phy or osc
+	*/
+
+	setbits_le32(&gpr->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
+	return set_clk_enet(ENET_50MHZ);
+#else
+	return set_clk_enet(ENET_125MHZ);
+#endif
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+#ifndef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+#endif
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0			0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
+
+#define USB_PHY_CTRL1			0xF0044
+#define USB_PHY_CTRL1_RESET		BIT(0)
+#define USB_PHY_CTRL1_COMMONONN		BIT(1)
+#define USB_PHY_CTRL1_ATERESET		BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
+
+#define USB_PHY_CTRL2			0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+#ifdef CONFIG_SPL_BUILD
+	.maximum_speed = USB_SPEED_HIGH,
+#else
+	.maximum_speed = USB_SPEED_SUPER,
+#endif
+	.base = USB1_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+	dwc3_uboot_handle_interrupt(index);
+	return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+	u32 RegData;
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL2);
+	RegData |= USB_PHY_CTRL2_TXENABLEN0;
+	writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		imx8m_usb_power(index, true);
+		dwc3_nxp_usb_phy_init(&dwc3_device_data);
+		return dwc3_uboot_init(&dwc3_device_data);
+	}
+	
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+		imx8m_usb_power(index, false);
+	}
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+	init_usb_clk();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+	env_set("board_name", "DDR3L-VAL");
+#else
+	env_set("board_name", "DDR4-VAL");
+#endif
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/imx8mq_val/spl.c b/board/freescale/imx8mq_val/spl.c
new file mode 100644
index 00000000000..7bc7b210991
--- /dev/null
+++ b/board/freescale/imx8mq_val/spl.c
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <spl.h>
+#include "../common/pfuze.h"
+#include <nand.h>
+#include "ddr/ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+	/* ddr init */
+	ddr_init(NULL);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+#else
+		ret = gpio_get_value(USDHC2_CD_GPIO);
+#endif
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return -ENODEV;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return -ENODEV;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	pmic_reg_read(p, PFUZE100_SW1ABVOL, &reg);
+	if ((reg & 0x3f) != 0x1c) {
+		reg &= ~0x3f;
+		reg |= 0x1c;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, reg);
+	}
+
+	pmic_reg_read(p, PFUZE100_SW1CVOL, &reg);
+	if ((reg & 0x3f) != 0x1c) {
+		reg &= ~0x3f;
+		reg |= 0x1c;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, reg);
+	}
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+
+	init_usb_clk();
+
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	init_uart_clk(0); /* Init UART0 clock */
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* Adjust pmic voltage VDD_DRAM to 1.0V for DRAM RUN >= 2400MHZ */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}