diff options
| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2015-04-22 10:59:50 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-05-04 09:25:12 -0700 |
| commit | fd3a78a538b2591a420f173faea442ae969ff623 (patch) | |
| tree | c4552ab9843cfc935647a06264f8131dddb48350 /board/freescale/t208xrdb/cpld.h | |
| parent | 1a56fcea9f47ce9184f4dafd3e856de2d85d47cd (diff) | |
board/t2080rdb: reset cs4315 phy
CS4315 PHY doesn't support phy-reset by software, it
needs to reset it by hardware via CPLD control.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t208xrdb/cpld.h')
| -rw-r--r-- | board/freescale/t208xrdb/cpld.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index 3f1533888d..9bd5247563 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -40,3 +40,6 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 #define CPLD_BOOT_SEL 0x80 + +/* RSTCON Register */ +#define CPLD_RSTCON_EDC_RST 0x04 |