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authorShengzhou Liu <Shengzhou.Liu@freescale.com>2015-03-27 15:48:34 +0800
committerYork Sun <yorksun@freescale.com>2015-05-04 09:24:31 -0700
commite8a7f1c32b55f48408a10cded2663b3f578d02e2 (patch)
tree0657a60ddc773e47b42b18bb39092d59b0489fbc /board/freescale/t102xrdb/eth_t102xrdb.c
parent1d0b59a9b049443397f484ad03b88c6314bc7ebb (diff)
powerpc/t1023rdb: Add T1023 RDB board support
T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. T1023RDB board Overview ----------------------- - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - one 1G RGMII port on-board(RTL8211F PHY) - one 1G SGMII port on-board(RTL8211F PHY) - one 2.5G SGMII port on-board(AQR105 PHY) - PCIe: Two Mini-PCIe connectors on-board. - SerDes: 4 lanes up to 10.3125GHz - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. - USB: one Type-A USB 2.0 port with internal PHY - eSDHC: support SD/MMC card and eMMC on-board - 256Kbit M24256 I2C EEPROM - RTC: Real-time clock DS1339 on I2C bus - UART: one serial port on-board with RJ45 connector - Debugging: JTAG/COP for T1023 debugging As well updated T1024RDB to add T1023RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix defconfig files] Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t102xrdb/eth_t102xrdb.c')
-rw-r--r--board/freescale/t102xrdb/eth_t102xrdb.c27
1 files changed, 24 insertions, 3 deletions
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index f611ff07e9..dd386bc3a9 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -1,6 +1,8 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -56,6 +58,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
+#ifdef CONFIG_T1024RDB
case 0x95:
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
@@ -63,10 +66,17 @@ int board_eth_init(bd_t *bis)
/* set 10G XFI with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
+#endif
+ case 0x6a:
+ case 0x6b:
case 0x77:
case 0x135:
/* set the on-board 2.5G SGMII AQR105 PHY */
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
+#ifdef CONFIG_T1023RDB
+ /* set the on-board 1G SGMII RTL8211F PHY */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
+#endif
break;
default:
printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
@@ -81,6 +91,14 @@ int board_eth_init(bd_t *bis)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
+ case PHY_INTERFACE_MODE_SGMII:
+#if defined(CONFIG_T1023RDB)
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+#elif defined(CONFIG_T1024RDB)
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+#endif
+ fm_info_set_mdio(i, dev);
+ break;
case PHY_INTERFACE_MODE_SGMII_2500:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
@@ -110,13 +128,16 @@ int board_eth_init(bd_t *bis)
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
- if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
- (port == FM1_DTSEC3)) {
+#if defined(CONFIG_T1024RDB)
+ if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
+ (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
+ (port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
fdt_setprop(fdt, offset, "phy-connection-type",
"sgmii-2500", 10);
fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
}
+#endif
}
void fdt_fixup_board_enet(void *fdt)