diff options
| author | Wolfgang Denk <wd@denx.de> | 2011-07-18 21:03:08 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-07-18 21:03:08 +0200 |
| commit | 1c6d00c2b5f090f5ae9b0d5cd9cf9a0adfdd2c77 (patch) | |
| tree | fa63ea5e17706836fdc6c0a137a1d15f8cf694cb /board/freescale/p2041rdb/cpld.h | |
| parent | a28afca57df7875f3334407bc47bd66b98701534 (diff) | |
| parent | 4f1d1b7d1e647b4e0ffd9b9feedd02110d078bdb (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/p2041rdb: Add p2041rdb board support
powerpc/85xx: Fix detection of P1017E
powerpc/mpc8548cds: Remove incorrect DDR_MSYNC_IN erratum define
Diffstat (limited to 'board/freescale/p2041rdb/cpld.h')
| -rw-r--r-- | board/freescale/p2041rdb/cpld.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/board/freescale/p2041rdb/cpld.h b/board/freescale/p2041rdb/cpld.h new file mode 100644 index 0000000000..3b24cb0480 --- /dev/null +++ b/board/freescale/p2041rdb/cpld.h @@ -0,0 +1,53 @@ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu <Mingkai.hu@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +typedef struct cpld_data { + u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ + u8 pcba_ver; /* 0x2 - PCBA Revision Register */ + u8 system_rst; /* 0x3 - system reset register */ + u8 wd_cfg; /* 0x4 - Watchdog Period Setting Register */ + u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */ + u8 por_cfg; /* 0x6 - POR Control Register */ + u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */ + u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */ + u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */ + u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */ + u8 fbank_sel; /* 0xb - Flash bank selection */ + u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ + u8 sw[1]; /* 0xd - SW2 Status */ +} __attribute__ ((packed)) cpld_data_t; + +#define SERDES_MUX_LANE_6_MASK 0x2 +#define SERDES_MUX_LANE_6_SHIFT 1 +#define SERDES_MUX_LANE_A_MASK 0x1 +#define SERDES_MUX_LANE_A_SHIFT 0 +#define SERDES_MUX_LANE_C_MASK 0x4 +#define SERDES_MUX_LANE_C_SHIFT 2 +#define SERDES_MUX_LANE_D_MASK 0x8 +#define SERDES_MUX_LANE_D_SHIFT 3 + +/* Pointer to the CPLD register set */ +#define cpld ((cpld_data_t *)CPLD_BASE) + +/* The CPLD SW register that corresponds to board switch X, where x >= 1 */ +#define CPLD_SW(x) (cpld->sw[(x) - 2]) + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) +#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) |