ENGR00117616: PATA support in u-boot.

PATA support in u-boot.

Signed-off-by: Terry Lv <r65388@freescale.com>

2 files changed, 241 insertions, 5 deletions

diff --git a/board/freescale/mx51_3stack/flash_header.S b/board/freescale/mx51_3stack/flash_header.S
index 794ab6b4e6..172220a0ad 100644
--- a/board/freescale/mx51_3stack/flash_header.S
+++ b/board/freescale/mx51_3stack/flash_header.S
@@ -108,6 +108,6 @@ MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
 MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
 MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
 dcd_data_end:
-image_len:		.word	0x40000
+image_len:		.word	0x80000
 //image_len:		.word	_end - _start
 #endif
diff --git a/board/freescale/mx51_3stack/mx51_3stack.c b/board/freescale/mx51_3stack/mx51_3stack.c
index 50aec8c2ed..8e315bd1da 100644
--- a/board/freescale/mx51_3stack/mx51_3stack.c
+++ b/board/freescale/mx51_3stack/mx51_3stack.c
@@ -159,6 +159,110 @@ static void setup_expio(void)
 	writew(reg, mx51_io_base_addr + PBC_SW_RESET);
 }
 
+#if defined(CONFIG_MXC_ATA)
+int setup_ata()
+{
+	u32 pad;
+
+	pad = (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH);
+
+	/* Need to disable nand iomux first */
+	mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, pad);
+
+	/* TO 2.0 */
+	mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, pad);
+
+	/* TO 1.0 */
+	mxc_request_iomux(MX51_PIN_NANDF_RB5, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB5, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D0, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D1, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D2, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D3, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D4, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D5, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D6, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D7, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D8, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D9, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D10, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D11, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D12, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D13, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D14, pad);
+
+	mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_NANDF_D15, pad);
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_I2C_MXC
 static setup_i2c(unsigned int module_base)
 {
@@ -214,11 +318,143 @@ static setup_i2c(unsigned int module_base)
 		break;
 	}
 }
+
+#define REV_ATLAS_LITE_1_0	   0x8
+#define REV_ATLAS_LITE_1_1	   0x9
+#define REV_ATLAS_LITE_2_0	   0x10
+#define REV_ATLAS_LITE_2_1	   0x11
+
+void setup_core_voltages(void)
+{
+	unsigned char buf[4] = { 0 };
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	if (is_soc_rev(CHIP_REV_2_0) <= 0) {
+		/* Set core voltage to 1.1V */
+		if (i2c_read(0x8, 24, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x18 fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x14;
+		if (i2c_write(0x8, 24, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x18 fail\n");
+			return;
+		}
+
+		/* Setup VCC (SW2) to 1.25 */
+		if (i2c_read(0x8, 25, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x1A;
+		if (i2c_write(0x8, 25, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
+			return;
+		}
+
+		/* Setup 1V2_DIG1 (SW3) to 1.25 */
+		if (i2c_read(0x8, 26, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x1A;
+		if (i2c_write(0x8, 26, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
+			return;
+		}
+
+		udelay(50);
+
+		/* Raise the core frequency to 800MHz */
+		writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
+	} else {
+		/* TO 3.0 */
+		/* Setup VCC (SW2) to 1.225 */
+		if (i2c_read(0x8, 25, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x19 fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x19;
+		if (i2c_write(0x8, 25, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x19 fail\n");
+			return;
+		}
+
+		/* Setup 1V2_DIG1 (SW3) to 1.2 */
+		if (i2c_read(0x8, 26, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1A fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0x1F)) | 0x18;
+		if (i2c_write(0x8, 26, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1A fail\n");
+			return;
+		}
+	}
+
+	if (i2c_read(0x8, 7, 1, buf, 3)) {
+		puts("setup_core_voltages: read PMIC@0x08:0x07 fail\n");
+		return;
+	}
+
+	if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) {
+		/* Set switchers in PWM mode for Atlas 2.0 and lower */
+		/* Setup the switcher mode for SW1 & SW2*/
+		if (i2c_read(0x8, 28, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0xF)) | 0x5;
+		buf[1] = (buf[1] & (~0x3C)) | 0x14;
+		if (i2c_write(0x8, 28, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
+			return;
+		}
+
+		/* Setup the switcher mode for SW3 & SW4*/
+		if (i2c_read(0x8, 29, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0xF)) | 0x5;
+		buf[1] = (buf[1] & (~0xF)) | 0x5;
+		if (i2c_write(0x8, 29, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
+			return;
+		}
+	} else {
+		/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
+		/* Setup the switcher mode for SW1 & SW2*/
+		if (i2c_read(0x8, 28, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1C fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0xF)) | 0x8;
+		buf[1] = (buf[1] & (~0x3C)) | 0x20;
+		if (i2c_write(0x8, 28, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1C fail\n");
+			return;
+		}
+
+		/* Setup the switcher mode for SW3 & SW4*/
+		if (i2c_read(0x8, 29, 1, buf, 3)) {
+			puts("setup_core_voltages: read PMIC@0x08:0x1D fail\n");
+			return;
+		}
+		buf[2] = (buf[2] & (~0xF)) | 0x8;
+		buf[1] = (buf[1] & (~0xF)) | 0x8;
+		if (i2c_write(0x8, 29, 1, buf, 3)) {
+			puts("setup_core_voltages: write PMIC@0x08:0x1D fail\n");
+			return;
+		}
+	}
+}
+
 #endif
 
 int board_init(void)
 {
-	int pad;
 	setup_soc_rev();
 
 	gd->bd->bi_arch_number = MACH_TYPE_MX51_3DS;	/* board id for linux */
@@ -230,6 +466,7 @@ int board_init(void)
 	setup_expio();
 #ifdef CONFIG_I2C_MXC
 	setup_i2c(I2C2_BASE_ADDR);
+	setup_core_voltages();
 #endif
 	return 0;
 }
@@ -243,7 +480,6 @@ int board_late_init(void)
 	int state = 0, boot_mode_switch = 0;
 #endif
 
-
 #if defined(CONFIG_FSL_ANDROID) && defined(CONFIG_MXC_KPD)
 	mxc_kpp_init();
 
@@ -321,7 +557,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	printf("Board: MX51 3STACK [");
+	printf("Board: MX51 3STACK ");
 
 	if (system_rev & CHIP_REV_2_0) {
 		printf("2.0 [");
@@ -345,7 +581,7 @@ int checkboard(void)
 	default:
 		printf("unknown");
 	}
-	printf("]]\n");
+	printf("]\n");
 	return 0;
 }