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authorKumar Gala <galak@kernel.crashing.org>2008-12-02 16:08:36 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2009-01-23 17:03:13 -0600
commit10795f42cb94e71bcb262b615084f69dd886399a (patch)
tree8954d541f7006c1838691799daca3bacb5667c1b /board/freescale/mpc8568mds
parentc953ddfd56b3ae3f28910fe3aed6de6968d1c9aa (diff)
85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/mpc8568mds')
-rw-r--r--board/freescale/mpc8568mds/law.c2
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index da7b6dcb722..a06ac2a0e14 100644
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -54,7 +54,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW(CONFIG_SYS_SRIO_MEM_BUS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 7a23b338a59..20f70fb520b 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -397,7 +397,7 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
@@ -450,7 +450,7 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);