diff options
author | Markus Klotzbuecher <mk@denx.de> | 2008-10-21 09:18:01 +0200 |
---|---|---|
committer | Markus Klotzbuecher <mk@denx.de> | 2008-10-21 09:18:01 +0200 |
commit | 50bd0057ba8fceeb48533f8b1a652ccd0e170838 (patch) | |
tree | ea1a183343573c2a48248923b96d316c0956727c /board/freescale/mpc8560ads | |
parent | 9dbc366744960013965fce8851035b6141f3b3ae (diff) | |
parent | f82642e33899766892499b163e60560fbbf87773 (diff) |
Merge git://git.denx.de/u-boot into x1
Conflicts:
drivers/usb/usb_ohci.c
Diffstat (limited to 'board/freescale/mpc8560ads')
-rw-r--r-- | board/freescale/mpc8560ads/ddr.c | 5 | ||||
-rw-r--r-- | board/freescale/mpc8560ads/law.c | 10 | ||||
-rw-r--r-- | board/freescale/mpc8560ads/mpc8560ads.c | 64 | ||||
-rw-r--r-- | board/freescale/mpc8560ads/tlb.c | 28 |
4 files changed, 55 insertions, 52 deletions
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 45372f42713..7850794d64f 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for CPO: diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index 3b8bd05ad12..7dd8f29588a 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 851fc5706a0..4fe1d85384c 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -217,7 +217,7 @@ typedef struct bcsr_ { void reset_phy (void) { #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR; + volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR; #endif /* reset Giga bit Ethernet port if needed here */ @@ -275,7 +275,7 @@ initdram(int board_type) #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* @@ -320,8 +320,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -341,10 +341,10 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ } else { /* @@ -359,7 +359,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */ udelay(200); /* @@ -380,52 +380,52 @@ local_bus_init(void) void sdram_init(void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CFG_OR2_PRELIM; - lbc->br2 = CFG_BR2_PRELIM; - lbc->lbcr = CFG_LBC_LBCR; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; + lbc->br2 = CONFIG_SYS_BR2_PRELIM; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); /* * Configure the SDRAM controller. */ - lbc->lsdmr = CFG_LBC_LSDMR_1; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_2; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_3; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_5; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -438,15 +438,15 @@ sdram_init(void) ************************************************************************/ long int fixed_sdram (void) { - #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; + #ifndef CONFIG_SYS_RAMBOOT + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; #if defined (CONFIG_DDR_ECC) ddr->err_disable = 0x0000000D; ddr->err_sbe = 0x00ff0000; @@ -455,14 +455,14 @@ long int fixed_sdram (void) udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #endif asm("sync; isync; msync"); udelay(500); #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 4fe2862f7d5..2ec3ccce97d 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -95,7 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -103,7 +103,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 7: 16K Non-cacheable, guarded * 0xf8000000 16K BCSR registers */ - SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), @@ -117,11 +117,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * Likely it needs to be increased by two for these entries. */ #error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_64M, 1), #endif |