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authorTsiChung Liew <Tsi-Chung.Liew@freescale.com>2008-10-24 12:59:12 +0000
committerJohn Rigby <jrigby@freescale.com>2008-11-03 09:45:59 -0700
commite4f69d1bd21a12049744989d2dd6b5199c9b8f23 (patch)
treef5e1e5d9517aefd8b071b5a4fd1fb0ec94cb943f /board/freescale/m5373evb
parent1b2708442224a551a0b865b52710306333888932 (diff)
ColdFire: Fix M5329EVB and M5373EVB nand issue
Fix compilation issue caused by a few mismatches. Provide proper nand chip select enable/disable in nand_hwcontrol() rather than in board_nand_init() just enable once. Remove redundant local nand driver functions - nand_read_byte(), nand_write_byte() and nand_dev_ready() to use common nand driver. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'board/freescale/m5373evb')
-rw-r--r--board/freescale/m5373evb/nand.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index d01b819ec89..3ebef059e14 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -41,19 +41,21 @@ DECLARE_GLOBAL_DATA_PTR;
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- u32 nand_baseaddr = (u32) this->IO_ADDR_W;
+ volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(SET_ALE | SE_CLE);
+ IO_ADDR_W &= ~(SET_ALE | SET_CLE);
+ *nCE &= 0xFFFB;
+
+ if (ctrl & NAND_NCE)
+ *nCE |= 0x0004;
if (ctrl & NAND_CLE)
IO_ADDR_W |= SET_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= SET_ALE;
- at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
@@ -67,10 +69,13 @@ int board_nand_init(struct nand_chip *nand)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- *((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
fbcs->csmr2 &= ~FBCS_CSMR_WP;
- /* set up pin configuration */
+ /*
+ * set up pin configuration - enabled 2nd output buffer's signals
+ * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
+ * to use nCE signal
+ */
gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
gpio->pddr_timer |= 0x08;
gpio->ppd_timer |= 0x08;