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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-10-16 15:01:15 +0200
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:03 +0200
commit6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch)
treeae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/freescale/m5235evb
parent71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff)
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/freescale/m5235evb')
-rw-r--r--board/freescale/m5235evb/m5235evb.c10
-rw-r--r--board/freescale/m5235evb/mii.c8
2 files changed, 9 insertions, 9 deletions
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index bd8a4e5e688..b9e61269c74 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -57,7 +57,7 @@ phys_size_t initdram(int board_type)
GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
- dramsize = CFG_SDRAM_SIZE * 0x100000;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -65,7 +65,7 @@ phys_size_t initdram(int board_type)
i--;
if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
- dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+ dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
/* Initialize DRAM Control Register: DCR */
sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
@@ -73,7 +73,7 @@ phys_size_t initdram(int board_type)
/* Initialize DACR0 */
sdram->dacr0 =
- SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
+ SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
asm("nop");
@@ -90,7 +90,7 @@ phys_size_t initdram(int board_type)
}
/* Write to this block to initiate precharge */
- *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_RE;
@@ -105,7 +105,7 @@ phys_size_t initdram(int board_type)
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
return dramsize;
diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c
index 1fd4d99c1e0..5fbbd667a19 100644
--- a/board/freescale/m5235evb/mii.c
+++ b/board/freescale/m5235evb/mii.c
@@ -49,7 +49,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -135,9 +135,9 @@ uint mii_send(uint mii_cmd)
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */
+#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -202,7 +202,7 @@ int mii_discover_phy(struct eth_device *dev)
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));