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authorMingkai Hu <Mingkai.Hu@freescale.com>2015-10-26 19:47:52 +0800
committerYork Sun <yorksun@freescale.com>2015-10-29 10:34:01 -0700
commitf3a8e2b7d41ca9039e934b5a59899dd57c577fa3 (patch)
tree7ef53f37bd79d91736b251bb49dde1354016b46a /board/freescale/ls1043ardb/ddr.h
parent8281c58fd46d095e28e60b2fb0ce84b4444896f8 (diff)
armv8/ls1043ardb: Add LS1043ARDB board support
LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Diffstat (limited to 'board/freescale/ls1043ardb/ddr.h')
-rw-r--r--board/freescale/ls1043ardb/ddr.h45
1 files changed, 45 insertions, 0 deletions
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
new file mode 100644
index 0000000000..b17eb80885
--- /dev/null
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo_override;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+#ifdef CONFIG_SYS_FSL_DDR4
+ {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,},
+ {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,},
+ {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,},
+#endif
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+#endif