diff options
| author | Madalin Bucur <madalin.bucur@oss.nxp.com> | 2020-11-04 15:09:17 +0200 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-12-10 13:56:39 +0530 |
| commit | 848a2efd142ab6d879b1afed0cdbfada30522fa7 (patch) | |
| tree | 32ef8b42f1aed1b1ff610cea82df8d7a497bd824 /board/freescale/corenet_ds | |
| parent | ccedd4ff8e359acfbf1877af14937a9e5045b25f (diff) | |
board: freescale: powerpc: add support for all RGMII modes
Make sure all RGMII internal delay modes are covered.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'board/freescale/corenet_ds')
| -rw-r--r-- | board/freescale/corenet_ds/eth_hydra.c | 6 | ||||
| -rw-r--r-- | board/freescale/corenet_ds/eth_p4080.c | 6 | ||||
| -rw-r--r-- | board/freescale/corenet_ds/eth_superhydra.c | 12 |
3 files changed, 24 insertions, 0 deletions
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 8112c12568d..6500c2fcf67 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -350,6 +350,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "emi1_rgmii"); break; default: @@ -449,6 +452,9 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * If DTSEC4 is RGMII, then it's routed via via EC1 to * the first on-board RGMII port. If DTSEC5 is RGMII, diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 650013bb6fc..df5a69bcba3 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -367,6 +367,9 @@ int board_eth_init(struct bd_info *bis) }; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fm_info_set_phy_address(i, 0); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, @@ -434,6 +437,9 @@ int board_eth_init(struct bd_info *bis) }; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fm_info_set_phy_address(i, 0); mdio_mux[i] = EMI1_RGMII; fm_info_set_mdio(i, diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index 35daa1e80f3..de7b692f3fe 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -317,6 +317,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "hydra_rg"); debug("Enabled MDIO node hydra_rg\n"); break; @@ -353,6 +356,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "hydra_rg"); debug("Enabled MDIO node hydra_rg\n"); break; @@ -557,6 +563,9 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the @@ -704,6 +713,9 @@ int board_eth_init(struct bd_info *bis) break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * FM1 DTSEC5 is routed via EC1 to the first on-board * RGMII port. FM2 DTSEC5 is routed via EC2 to the |