diff options
| author | York Sun <yorksun@freescale.com> | 2011-03-02 14:24:11 -0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-03-05 10:13:50 -0600 |
| commit | f5b6fb7c1b988cdec8db9e96dd05d1df46c22e6b (patch) | |
| tree | 8d9bac65135dedd1eb7c02308a1922057747aa32 /board/freescale/corenet_ds/ddr.c | |
| parent | 8e29ebabf825ee0c85cb0c93d6aa495cc54811ab (diff) | |
powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/corenet_ds/ddr.c')
0 files changed, 0 insertions, 0 deletions